Sum of Addends Logic Circuit with Faithful Rounding
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Solution Overview
Problem
The complexity of determining the effect of truncation in sum of addends operations in integrated circuit design leads to increased hardware implementation costs and power consumption, especially with larger multipliers, due to the need for error statistics and multiple iterations during RTL synthesis.
Innovation Solution
A method for deriving a logic circuit that performs a sum of addends operation with faithful rounding by determining which bits to discard and a constant to include, optimizing the number of columns and bits to remove while maintaining a known error profile, thereby reducing hardware complexity and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If truncation is applied to reduce the number of bits in sum of addends operation, then hardware implementation cost and silicon area are reduced, but determining the effect of truncation becomes complex and time-consuming
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing truncation constants in lookup tables before the actual multiplication operation. The RTL synthesis tool queries these pre-computed tables to determine the appropriate constant to add when truncating bits, eliminating the need for complex real-time error analysis and iterations during synthesis.
Solution Approach 2:
The patent introduces an intermediary mechanism - a lookup table containing pre-computed truncation constants - that mediates between the truncation operation and the error compensation requirement. This intermediary structure provides the correct compensation value without requiring complex analysis of the truncation effects on error statistics.
2Measurement precision
If full summation is performed to maintain precision, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent changes the parameter of truncation precision by dynamically selecting how many bits to truncate based on the specific multiplication operation. Instead of always performing full summation, the system adjusts the precision parameter adaptively - truncating less significant bits when appropriate and compensating with pre-computed constants, thus reducing gate count while maintaining required precision.
Solution Approach 2:
The patent applies partial action by performing summation only on the necessary significant bits rather than all bits. By truncating the least significant columns and adding a compensation constant, the system performs a partial summation that is sufficient for the required precision level, reducing the number of gates needed compared to full summation of all bits.
3Manufacturing precision
If multiple iterations are performed during RTL synthesis to optimize truncation, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent eliminates iterative optimization by performing the error compensation calculation in advance and storing results in lookup tables. During RTL synthesis, the tool simply queries the pre-computed table rather than performing multiple iterations to determine the optimal truncation constant, dramatically reducing synthesis time while maintaining precision.
Solution Approach 2:
The lookup table structure enables the synthesis tool to self-determine the correct truncation constant through simple table lookup without requiring iterative optimization algorithms. The pre-computed tables contain all necessary compensation values, allowing the synthesis process to automatically select the appropriate constant based on the specific operation parameters.
Data Source
AI summary
A method is provided for a synthesizing In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimization constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesized in RTL (31) before manufacturing an integrated circuit.