Vector Instruction for Complex Conjugate Multiplication
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Solution Overview
Problem
Current computer processors face inefficiencies in performing complex conjugate multiplication operations, particularly in digital signal processing, due to the need for sequential execution of instructions in existing SIMD microarchitectures.
Innovation Solution
The implementation of a vector friendly instruction format that supports vector operations, allowing for the execution of complex conjugate multiplication through a single instruction, utilizing a generic vector friendly instruction format with specific fields and templates that enable efficient processing of complex data types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing SIMD microarchitectures are used to perform complex conjugate multiplication, then the operation can be completed, but it requires sequential execution of multiple instructions which reduces processing speed
Solution Approach 1:
The patent combines multiple sequential instructions (multiply, add, accumulate) into a single vector instruction that performs complex conjugate multiplication with accumulation in one operation. This merging of operations eliminates the need for sequential execution and improves processing speed while maintaining clarity in the instruction set.
Solution Approach 2:
The vector instruction designed in the patent serves multiple functions simultaneously: it performs complex conjugate multiplication, accumulation, and result storage in a single operation. This multi-functionality approach allows the same instruction to handle what would traditionally require separate instructions, thereby improving execution speed without increasing device complexity.
2Productivity
If multiple sequential instructions are used for multiply-accumulate operations, then compatibility with existing SIMD microarchitectures is maintained, but processing efficiency is reduced
Solution Approach 1:
The patent prepares the instruction format and data layout in advance to enable direct execution of complex conjugate multiplication with accumulation. By designing the vector instruction to accept properly formatted complex data and perform all necessary operations in one step, the system eliminates the time loss associated with sequential instruction execution while maintaining compatibility with existing SIMD architectures.
3Loss of time
If a single instruction performs complex conjugate multiplication, then execution time is reduced, but the instruction format complexity increases
Solution Approach 1:
The patent segments the complex conjugate multiplication operation into distinct field components (real parts, imaginary parts, accumulation terms) that can be processed independently within the single instruction. This segmentation allows the instruction format to be structured in a systematic way that reduces complexity while enabling comprehensive processing of all necessary computational elements in one execution cycle.
Data Source
AI summary
An apparatus and method for multiplying packed real and imaginary components of complex numbers are described. A processor embodiment includes: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes: multiplier circuitry to select real and imaginary data elements in the first source register and second source, multiply each selected imaginary data element in the first source register with a selected real data element in the second source register, and multiply each selected real data element in the first source register with a selected imaginary data element in the second source register to generate a plurality of imaginary products; adder circuitry to add a first subset of the plurality of imaginary products and subtract a second subset of the plurality of imaginary products to generate a first temporary result, and to add a third subset of the plurality of imaginary products and subtract a fourth subset of the plurality of imaginary products to generate a second temporary result; and accumulation circuitry to combine the first temporary result with first data from a destination register to generate a first final result, combine the second temporary result with second data from the destination register to generate a second final result, and store the first final result and second final result back in the destination register.