Fast Vector Multiplication Circuit for Neural Network Accelerators
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Solution Overview
Problem
Conventional systems performing convolution calculations in neural networks are computationally intensive and power-consuming due to limited parallelization capabilities of processors, leading to increased complexity and power consumption during matrix multiplications.
Innovation Solution
A fast vector multiplication and accumulation circuit is introduced, comprising a scheduler, a self-accumulating adder, and an adder, which arranges multiplicands into scheduled operands based on multipliers, utilizing a compressor, delay elements, and a shifter to enhance vector parallelism and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a processor repeatedly calculates individual sums and products for convolution calculations using a direct multiplier, then the computation can be performed with standard architecture, but the computational complexity and power consumption are greatly increased
Solution Approach 1:
The multiplicand vector is segmented into multiple sub-vectors, and the multiplication process is divided into stages where partial products are accumulated incrementally. This segmentation allows the complex N-element multiplication to be broken down into manageable chunks that can be processed with simpler circuitry at each stage.
Solution Approach 2:
The patent introduces a temporal dimension by processing multiplications in multiple clock cycles rather than requiring all N multiplications to occur simultaneously. This transforms the spatial complexity of parallel multiplication into temporal complexity, allowing the use of simpler sequential accumulation logic.
2Measurement precision
If a processor repeatedly calculates individual sums and products for convolution calculations, then the calculation can be completed accurately, but the power consumption is greatly increased
Solution Approach 1:
By segmenting the multiplication process into stages that accumulate partial products, the circuit avoids the need for full parallel multiplication hardware that would consume excessive power. Each stage processes a subset of elements, reducing the instantaneous power requirement while maintaining final calculation accuracy.
Solution Approach 2:
The accumulator continuously updates the partial sum across multiple clock cycles, keeping the accumulation logic actively engaged throughout the computation process. This continuous action eliminates the need for repeated full-circuit activation, reducing overall power consumption while ensuring accurate final results.
3Ease of manufacture
If the degree of parallelization is limited due to processor architecture, then the system can maintain standard architecture, but the computational efficiency is reduced
Solution Approach 1:
The patent achieves enhanced parallelism by utilizing temporal parallelism across multiple clock cycles rather than relying solely on spatial parallelism within a single cycle. This allows the circuit to process multiple elements sequentially with simple logic, achieving computational efficiency comparable to more complex parallel architectures.
Solution Approach 2:
The scheduler prepares and organizes the multiplication operations in advance, arranging elements in an optimal sequence for the accumulation process. This preliminary organization enables the simple accumulator circuit to process data efficiently without requiring complex real-time control logic during the actual computation.
Data Source
AI summary
A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.