Matrix Multiplication Circuit Module Using Time-Multiplexed Row-Column Calculation
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Solution Overview
Problem
Current technologies face challenges in efficiently performing matrix multiplication, particularly in hardware-based implementations, which can be complex and occupy significant space due to the need for multiple multiplication units.
Innovation Solution
A circuit module and method utilizing a row-column calculation unit with a multiplication unit and an addition unit, where electrical signals representing matrix elements are inputted in predetermined timing sequences to perform row-column multiplication calculations, reducing the number of multiplication units and simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple multiplication units are used in hardware-based matrix multiplication, then calculation speed is improved, but device complexity and space occupation increase
Solution Approach 1:
The patent segments the matrix multiplication process into distinct phases: input phase (receiving electrical signals representing matrix elements), multiplication phase (computing products), and accumulation phase (summing products). This temporal segmentation allows a single multiplication unit to be reused across different phases, reducing the need for multiple simultaneous multiplication units while maintaining calculation throughput.
Solution Approach 2:
The patent implements periodic action by using predetermined timing sequences to control the operation of the multiplication unit. The unit operates in periodic cycles: during first time periods it performs multiplication, during second time periods it remains idle or prepares for next operations. This periodic operation pattern allows time-multiplexed usage of the multiplication unit, reducing hardware complexity while achieving required calculation speed through efficient time utilization.
2Productivity
If multiple multiplication units are used in hardware-based matrix multiplication, then calculation speed is improved, but space occupation increases
Solution Approach 1:
The patent merges the functions of multiple multiplication units into a single multiplication unit by combining the multiplication operation with temporal control mechanisms. The single unit handles all multiplication tasks sequentially according to predetermined timing sequences, eliminating the need for multiple parallel multiplication units and thereby reducing circuit space occupation while maintaining overall calculation throughput.
Solution Approach 2:
The patent transitions from a spatial dimension solution (using multiple parallel multiplication units) to a temporal dimension solution (using a single multiplication unit with predetermined timing sequences). By adding the time dimension to the operation control, the system achieves the required calculation speed without increasing spatial occupation, effectively trading space for time in the hardware architecture.
3Device complexity
If electrical signals are inputted in predetermined timing sequences, then circuit complexity is reduced, but calculation time increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the timing sequences for inputting electrical signals and controlling the multiplication unit operations before actual matrix multiplication begins. These predetermined timing sequences optimize the workflow and minimize idle time, ensuring that the single multiplication unit is efficiently utilized without excessive calculation delays, thus balancing circuit simplification with acceptable calculation time.
Data Source
AI summary
A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.