Mixed Radix FFT on GPUs Using Parallel Radix-r Blocks
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Solution Overview
Problem
Current methods for performing mixed radix fast Fourier transforms (FFTs) on central processing units (CPUs) are inefficient due to repetitive calculations and do not fully utilize the processing power and memory available on graphics processing units (GPUs, limiting the performance of arbitrary length-based FFT algorithms and bit reversals.
Innovation Solution
Implementing a parallel method for mixed radix FFTs on GPUs using multiple execution units (EUs) and single instruction, multiple data (SIMD) features, which factorizes input data into radix-r blocks and performs bit-reversal operations in parallel, optimizing memory usage through lookup tables stored in registers, shared local memory, or DRAM based on data length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mixed radix FFT calculations are performed on CPUs using traditional sequential methods, then the algorithms can handle arbitrary length input data, but the processing speed is slow due to repetitive calculations and inability to utilize parallel processing capabilities
Solution Approach 1:
The patent segments the input data into multiple radix-r blocks and processes each block independently in parallel. The factorization of N into r1×r2×...×rk allows the FFT to be divided into multiple stages, where each stage processes smaller sub-problems independently. This segmentation enables the GPU to utilize its massive parallel processing capability while maintaining the correctness of the overall FFT computation.
Solution Approach 2:
The patent transitions from sequential CPU processing to parallel GPU processing by utilizing the spatial dimension of parallel computation. Multiple execution units (EUs) and single instruction, multiple data (SIMD) features are employed to process multiple data points simultaneously across different parallel dimensions, dramatically increasing processing throughput.
2Productivity
If traditional CPU-based FFT methods are used, then implementation is straightforward, but the processing performance is limited due to lack of parallel processing and inefficient memory utilization
Solution Approach 1:
The patent performs preliminary factorization of the input length N into radix components (r1×r2×...×rk) before the main FFT computation. Lookup tables are pre-computed and stored in memory for efficient access during the parallel processing stage. This preliminary preparation enables the subsequent parallel execution to proceed efficiently without complex runtime computations.
Solution Approach 2:
The patent introduces lookup tables as intermediary structures that store pre-computed values needed for the FFT computation. These tables serve as a bridge between the input data and the parallel processing units, enabling efficient data transformation without requiring complex real-time computations during the main processing stage.
3Productivity
If arbitrary length FFT algorithms are implemented on GPUs, then parallel processing capability can be utilized, but memory management becomes complex requiring optimization through lookup tables in different memory structures
Solution Approach 1:
The patent optimizes memory usage by placing different types of data in different memory locations based on their access patterns and size requirements. Lookup tables are stored in global memory for large datasets, while smaller frequently-accessed data are placed in shared memory or registers. This local optimization of memory placement reduces access latency and improves overall processing efficiency.
Solution Approach 2:
The patent dynamically adjusts memory allocation strategies based on the size of the input data and the specific radix-r blocks being processed. Memory structure selection (registers, shared memory, or global memory) is changed based on data length thresholds, optimizing the balance between memory capacity and access speed for different problem sizes.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.