Montgomery Multiplication Circuit Segmentation
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Solution Overview
Problem
The challenge lies in efficiently performing modular multiplication of large binary numbers, which exceeds the computing capacity of microprocessors, leading to increased response time and current consumption, particularly in encryption applications like contactless chip cards.
Innovation Solution
An electronic circuit method that optimizes modular multiplication by decomposing numbers into smaller digits, using a main loop with sub-loops to calculate partial results efficiently, employing Carry-Save Adders and multiplexers to minimize cycle time and size, and utilizing a combinatory logic circuit to produce partial results in less than half a processor cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If modular multiplication is performed on large binary numbers (512 bits) using a microprocessor, then the calculation can be executed, but the response time increases and current consumption increases due to the need to decompose large numbers into smaller slices
Solution Approach 1:
The patent decomposes large 512-bit numbers into smaller 64-bit slices that can be processed by the microprocessor. The main loop iterates L/k times (where k=64) to process each slice, and the first sub-loop decomposes each k-bit number into p-bit digits for parallel processing. This segmentation allows the microprocessor to handle large number multiplication by breaking it into manageable chunks, directly resolving the contradiction between handling large numbers and maintaining fast response time.
2Use of energy by stationary object
If modular multiplication circuit size is reduced to minimize product size, then current consumption decreases, but the computing capacity is reduced making it harder to handle large numbers
Solution Approach 1:
The circuit processes large numbers by segmenting them into k-bit slices (64 bits) that match the microprocessor's native word size. This allows the circuit to maintain a compact design that consumes less power while still achieving the required computing capacity through iterative processing of slices in the main loop, rather than requiring a single large processing unit.
Solution Approach 2:
The patent employs iterative loops (main loop with L/k iterations and first sub-loop with k/p iterations) that continuously process slices of the large numbers. This continuous processing approach allows the circuit to maintain high computing capacity for large number operations while keeping the hardware footprint small, as the same circuit resources are reused across multiple iterations rather than requiring dedicated hardware for each bit position.
3Loss of time
If the number of iterations is reduced to decrease response time, then processing speed improves, but the precision of calculating partial results may be compromised
Solution Approach 1:
The patent segments the calculation into two distinct phases: the first sub-loop calculates the least significant p bits of each digit mi with high precision, and the second sub-loop calculates the remaining partial results. This segmentation allows the algorithm to achieve both speed (by processing p bits per iteration instead of 1 bit) and precision (by systematically handling all bit positions across two sub-loops).
Solution Approach 2:
The first sub-loop performs preliminary calculation of the least significant p bits of each digit mi before the second sub-loop calculates the remaining partial results. This preliminary action ensures that the foundation of the calculation is established with full precision, allowing the subsequent loop to efficiently complete the calculation without compromising overall accuracy, thus achieving both speed and precision goals.
Data Source
AI summary
Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being k-bit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first sub-loop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into p-bit digits. Starting each sub-loop iteration, the p bits of the current digit of mi are simultaneously produced. A second sub-loop calculates and sums the remaining partial results of XYi+miM+R using mi from the first sub-loop.