Frequency Synthesis Using Primitive Integer Ratios and Common Reference Clock
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Solution Overview
Problem
Conventional fractional-N frequency synthesizers face challenges in determining divisor ratios, especially when the frequency of the data stream is unknown, leading to suboptimal performance and difficulty in supporting multiple protocol-dependent rates with a single reference clock without compromising jitter performance.
Innovation Solution
A Common Reference Ratio (CRR) module generates integer divisor ratios for a Clock Synthesis Unit using a single common reference clock, calculating a greatest common denominator and primitive ratio of integers for each desired output frequency, allowing for the creation of synthesized frequencies with minimal jitter across multiple protocol-dependent rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional fractional-N frequency synthesizers are used to support multiple protocol-dependent rates with a single reference clock, then the system complexity is reduced, but the jitter performance deteriorates due to difficulty in determining optimal divisor ratios
Solution Approach 1:
The patent pre-calculates and stores optimal divisor ratios for multiple protocol-dependent rates before operation. The system accepts reference clock frequencies and desired output frequencies, calculates raw ratios of integers, reduces them to primitive ratios by dividing by GCD, and stores these pre-determined ratios for quick retrieval during operation, eliminating real-time calculation complexity while maintaining precision
Solution Approach 2:
The patent introduces a Common Reference Ratio (CRR) module as an intermediary component that bridges the reference clock and the Clock Synthesis Unit. This module receives pre-calculated divisor ratios and translates them into operational parameters for the frequency synthesizer, enabling the system to switch between multiple protocol rates while maintaining optimal jitter performance through pre-optimized division ratios
2Manufacturing precision
If multiple reference clocks are used for different protocol-dependent rates, then the jitter performance is maintained, but the device complexity increases
Solution Approach 1:
The patent makes the single reference clock universal by pre-calculating optimal divisor ratios that work across multiple protocol-dependent rates. The CRR module and divisor ratio storage system enable one reference clock to serve multiple functions and support various data rates (such as 622.080 Mbps, 155.520 Mbps, 77.760 Mbps, etc.) without requiring separate reference clocks for each protocol, thereby maintaining jitter performance while reducing device complexity
Solution Approach 2:
The patent changes the operational parameters of the frequency synthesizer by dynamically adjusting the divisor ratios based on the selected protocol rate. Instead of changing the reference clock frequency or using multiple reference clocks, the system maintains a constant reference clock and varies only the division ratios (N and D values) to achieve different output frequencies, simplifying the overall system architecture
3Measurement precision
If fractional divisor ratios are used to achieve precise frequency synthesis, then the frequency accuracy is improved, but the system becomes more complex due to difficulty in determining optimal ratios
Solution Approach 1:
The patent performs preliminary calculation of fractional divisor ratios offline and stores them in a accessible memory structure. The system accepts reference clock frequency (fref) and desired output frequency (fout), calculates the raw ratio N/D = fout/fref, reduces it to primitive form by dividing both N and D by their GCD, and stores these pre-computed values. This eliminates the need for complex real-time fractional arithmetic while maintaining frequency accuracy
Solution Approach 2:
The patent replaces complex mechanical or hardware-based frequency division mechanisms with a software-based pre-calculation and lookup approach. Instead of using complex fractional-N synthesizer hardware that requires real-time determination of optimal divisor ratios, the system uses pre-computed ratios stored in memory, substituting hardware complexity with simpler storage and retrieval operations
Data Source
AI summary
A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1≦i≦k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that:foi=NprawiDprawi×fri.A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integersNpiDpiis found for each raw ratio of integers, such that:Npi=NprawiGCD(Nprawi,Dprawi);and,Dpi=DprawiGCD(Nprawi,Dprawi).Using the common clock frequency value (fcr), each primitive ratio of integers, each reference frequency value, and each GCD, a final ratio of integers Ncri and Dcri,C·(NcriDcri),is calculated for each synthesized frequency value, where C is an integer value.