Arithmetic Processing Device Instruction Overlap Control
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Solution Overview
Problem
Existing arithmetic processing devices face challenges in improving throughput when issuing two instructions, particularly due to difficulties in overlapping instructions with different execution cycles, leading to reduced efficiency and potential bottlenecks in pipeline operations.
Innovation Solution
The implementation of an instruction issuance control unit that utilizes issuance suppression signals and fetchable instruction detection units to manage and overlap pipeline operations, allowing partial overlap of composite multi-cycle operations and shared complete pipeline operations, thereby enhancing throughput by optimizing resource usage and reducing waiting times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two instructions are issued with overlapping execution, then throughput is improved, but resource conflicts and scheduling complexity increase
Solution Approach 1:
The patent implements dynamic instruction issuance control that adapts to the execution state of previous instructions. The control unit monitors whether a previous instruction is a composite multi-cycle operation and dynamically determines the timing for issuing the next instruction, allowing the system to optimize throughput while managing complexity through adaptive rather than static scheduling rules
Solution Approach 2:
The patent applies preliminary action by detecting the type of previous instruction (composite multi-cycle operation vs. shared complete pipeline operation) before issuing the next instruction. This advance detection allows the system to pre-determine appropriate issuance timing and avoid resource conflicts, resolving the contradiction between improving throughput through overlap and managing scheduling complexity
2Productivity
If instructions with long latencies are overlapped, then processing efficiency is improved, but resource sharing conflicts increase
Solution Approach 1:
The patent detects the instruction type in advance (whether it is a composite multi-cycle operation with long latency) and determines the appropriate issuance timing for subsequent instructions before resource conflicts can occur. This preliminary detection and timing determination ensures that instructions with long latencies can be overlapped safely while maintaining resource sharing reliability
Solution Approach 2:
The control unit continuously monitors the execution state and completion status of previous instructions, using this feedback to dynamically adjust the issuance timing of next instructions. This feedback mechanism ensures that resource sharing conflicts are avoided while still allowing maximum overlap of instructions with different latency characteristics
Data Source
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AI summary
An arithmetic processing device includes: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural, staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; a second instruction, execution, unit configured to execute a second instruction; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the second instruction are partly overlapped.