Concurrent Instruction Execution TRIZ Cases
- Serial Bus Split Transactions for NOR Flash Latency
Split transactions pipeline operations on a serial bus, reducing dummy cycles and doubling read throughput in NOR Flash systems.
- Microprocessor Register Scoreboard With Time Counter For Static Dispatch
A register scoreboard paired with a time counter dispatches instructions to an execution pipeline based on preset execution times.
- FIFO Instruction Reordering for Latency Reduction
Segments FIFO instructions into independent groups and reorders them based on path length metrics to resolve scheduling constraints.
- SoC Update Control Unit Synchronizing IP Block Data Processing
A centralized update control unit coordinates timing between master and slave IP blocks to prevent synchronization delays in SoC data rendering.
- Dual Branch Format for Microprocessor Pipeline Optimization
A dual branch processing method routes primary and secondary branch instructions through distinct hardware paths to optimize microprocessor instruction throughput.
- Processor Instruction Scheduling via Dynamic Reordering and Fusion
Dynamic instruction reordering and fusion reduce temporal latencies in processor pipelines.
- GPU Compute Optimization via Unified Shader Architecture
Unified shader cores and hierarchical segmentation maximize parallel processing efficiency while managing coordination complexity.
- Hard Negative Mining via Score History for DNN Training
A deep neural network training method uses score history to select hard negative samples for each epoch.
- Reduced-Width VLIW Processor Using Register Renaming for Atomic Commit
Register renaming enables atomic commit in reduced-width VLIW processors, lowering power consumption and cost while maintaining compiler compatibility.
- Dependence Matrix Segmentation for Load Miss Queue Tracking
Segmenting the dependence matrix into issue and load miss portions allows prompt instruction deallocation while maintaining consumer tracking.
- Heuristic Invalidation of Non-Useful OSC History Table Entries
A heuristic method invalidates non-useful entries in an operand store compare history table using a useless prediction counter.
- Branch Instruction Prediction Accuracy via Method Selection
A branch instruction processing system selects the highest accuracy prediction method from multiple preset approaches to improve processor efficiency.
- Retire Queue Compression for Out-of-Order Processor Performance
Control logic compresses multiple instruction operations into single retire queue entries to improve storage efficiency.
- Vector Execution Circuitry Address Hazard Detection
Execution circuitry detects address hazards during vector loop iterations to adjust processing levels.
- Precise-restartable Parallel Program Execution
A multiprocessor system enforces a total ordering of computational operations to establish a consistent architectural state for precise restartability.
- Asynchronous Pipeline Merging via Bitwise Vector Arbitration
Merge circuitry uses bitwise logical operations on logging bit vectors to select completed transactions for output pipelines.
- Entropy Decoding Context Pre-fetch and Miss Handling
Pre-fetching candidate contexts into a buffer breaks data dependency chains, reducing latency during video frame decoding.