Dual Branch Format for Microprocessor Pipeline Optimization
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Solution Overview
Problem
Microprocessors face bottlenecks in processing branch instructions due to the need for additional adder logic and multiple predictor table write ports, which increase complexity, cost, and hardware size, while existing branch prediction methods do not effectively address delays in conditional branch execution.
Innovation Solution
A branch processing method that assigns branch instructions as primary or secondary information, routing them through different pipeline paths with varying hardware complexity, and using two write queues to manage updates to branch prediction tables, reducing the need for additional hardware and optimizing instruction bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple predictor table write ports are added to handle updates from two branch execution units, then update capability is improved, but device complexity and hardware size increase
Solution Approach 1:
The patent segments the branch instruction processing into two distinct paths: a first path with adder logic for calculating target addresses, and a second path without adder logic. This segmentation allows the system to handle two branches per cycle without requiring multiple write ports to predictor tables, as the segmented processing reduces the update burden on any single port.
Solution Approach 2:
The patent introduces a new dimension of processing by creating parallel paths with different hardware characteristics. Instead of increasing write port capacity in the traditional vertical dimension, the system adds horizontal processing paths, where the second path compensates for the limited write port capacity by pre-processing branch information without requiring adder logic.
2Measurement precision
If adder logic is added for each branch to check target addresses, then branch processing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies local quality by providing adder logic only in the first path where it is most needed for accurate target address calculation, while the second path operates without adder logic. This localized application of complex hardware reduces overall device complexity while maintaining necessary precision where required.
Solution Approach 2:
The patent implements partial action by providing complete adder logic for only one branch path rather than duplicating it for both paths. The second path performs partial processing without the full adder logic, which is sufficient for its intended purpose of handling branches that don't require full target address verification.
3Productivity
If the pipeline is optimized to decode and execute two branches per clock cycle, then instruction throughput is improved, but the amount of hardware required increases
Solution Approach 1:
The patent merges the processing of two branches into a unified pipeline structure with shared components. The two paths share common infrastructure such as the branch order table and predictor tables, and the write ports are shared between both paths. This merging allows high throughput without proportionally increasing hardware quantity.
Solution Approach 2:
The patent creates universal hardware components that serve multiple functions. The write ports to predictor tables handle updates from both branch execution units, and the branch order table manages instructions from both paths. This multi-functionality reduces the total hardware required compared to having dedicated components for each branch path.
Data Source
AI summary
In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.