Serial Bus Split Transactions for NOR Flash Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing systems with serial buses, such as those used in automobile electronics, face limitations in increasing data throughput due to the need to maintain separate buses for command and data transactions, leading to inefficiencies in NOR Flash memory systems with latency issues.
Innovation Solution
Implementing split transactions on a serial bus, where a host device initiates and completes operations during latency periods, allowing for pipelined transactions and asynchronous data transfer, thereby optimizing the use of the serial bus and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speed is increased to reduce command/address/data time, then data throughput is improved, but the number of dummy cycles increases due to constant latency period
Solution Approach 1:
The transaction is divided into two separate phases: an initiation phase where the command and address are issued, and a completion phase where the data is transferred. This segmentation allows the host to issue multiple initiation commands in parallel during the latency period of previous transactions, effectively utilizing the dummy cycles that were previously wasted.
Solution Approach 2:
The host device issues initiation commands in advance during the latency period of previous transactions, before the data is actually ready to be transferred. This preliminary action allows the system to pipeline multiple transactions, so that by the time data becomes available, the transaction initiation has already been completed and the data can be transferred immediately without waiting for dummy cycles.
2Productivity
If separate buses are used for command/address and data transactions, then data throughput can be increased, but device pin count increases
Solution Approach 1:
The serial bus is designed to perform multiple functions: it can transmit commands, addresses, and data bidirectionally using the same physical medium. The bus operates in different modes (initiation mode and completion mode) to handle different types of transactions, eliminating the need for separate dedicated buses for commands and data while maintaining high throughput through pipelined operations.
Solution Approach 2:
The patent introduces a time dimension to the single bus architecture by implementing pipelined transactions. Instead of requiring spatial separation through multiple buses, the system uses temporal separation where different types of data (commands, addresses, data) are transmitted at different times over the same bus, achieving the functionality of separate buses without the pin count penalty.
3Reliability
If serial clock is kept active during latency periods, then transaction completion is maintained, but power consumption increases
Solution Approach 1:
The serial clock is activated only during specific periods when transactions are actively being initiated or completed, and is deactivated during the latency periods in between. This periodic activation pattern maintains reliable transaction completion when needed while significantly reducing power consumption during idle latency periods when no data transfer is occurring.
Data Source
AI summary
A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.