Microprocessor Register Scoreboard With Time Counter For Static Dispatch
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Solution Overview
Problem
Current out-of-order superscalar microprocessors face challenges with high power consumption and complex design due to dynamic scheduling of instructions, which complicates data dependency resolution and resource arbitration, while alternative VLIW processors have diminished interest due to complexity and weak performance.
Innovation Solution
Implementing a microprocessor with a register scoreboard and time counter for static scheduling of instructions, where instructions are dispatched to an execution pipeline based on preset execution times derived from a time count, ensuring no data dependencies and resource availability, thereby reducing complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order superscalar microprocessors use dynamic scheduling of instructions, then instruction execution flexibility and performance are improved, but power consumption and design complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the optimal execution time for each instruction in the register scoreboard before execution begins. The time counter is pre-configured with maximum values for different instruction types, allowing the scheduler to determine execution times in advance rather than dynamically during execution. This eliminates the need for complex real-time arbitration while maintaining out-of-order execution capability.
2Productivity
If out-of-order superscalar microprocessors implement dynamic scheduling, then instruction throughput is improved, but power consumption increases due to complex arbitration operations
Solution Approach 1:
The patent extracts the complex dynamic arbitration logic from the execution pipeline and replaces it with a simplified time-based scheduling mechanism. By storing predetermined execution times in the register scoreboard and using a simple time counter for comparison, the patent removes the power-hungry arbitration units while preserving the ability to execute multiple instructions out-of-order based on their predetermined time slots.
3Device complexity
If VLIW processors are used to simplify design, then device complexity is reduced, but performance and compiler complexity increase
Solution Approach 1:
The patent inverts the traditional approach by applying static scheduling concepts (typically associated with simpler architectures) to an out-of-order execution pipeline. Instead of using complex dynamic scheduling to achieve high performance, the patent uses predetermined execution times stored in the register scoreboard to enable out-of-order execution with simplified logic, effectively achieving VLIW-like simplicity while maintaining superscalar performance through the time-based dispatch mechanism.
Data Source
AI summary
A processor includes a time counter and a register scoreboard and operates to statically dispatch instructions with preset execution times based on a write time of a register in the register scoreboard and a time count of the time counter provided to an execution pipeline.