SoC Update Control Unit Synchronizing IP Block Data Processing

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Solution Overview

Problem

System-on-chip (SoC) technologies face challenges in processing operations efficiently and accurately, particularly in synchronizing updates of control information across functional blocks, leading to potential delays in data processing and image rendering.

Innovation Solution

The implementation of a system-on-chip with a slave intellectual property (IP) block and a master IP block, along with an update control unit, which processes data based on control information and synchronizes updates based on correlations between processing results from different blocks, ensuring timely and accurate data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If control information is updated independently in each functional block, then each block can process data autonomously, but synchronization delays occur and processing accuracy decreases

Engineering Contradiction:
Improvedata processing speedVSAvoidprocessing accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where functional blocks exchange information about their processing results and update status. The update control unit receives feedback signals from multiple functional blocks and uses this information to determine optimal update timing, ensuring that control information is updated only when all relevant blocks are ready, thus maintaining both speed and accuracy.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent merges the update control functions from individual functional blocks into a centralized update control unit that coordinates updates across all blocks. This unified control mechanism consolidates the update decisions, preventing independent updates that could cause synchronization issues while maintaining the autonomous processing capability of each block.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If control information is updated frequently to reflect processing results, then processing accuracy improves, but system complexity increases due to coordination requirements

Engineering Contradiction:
Improveprocessing accuracyVSAvoidupdate coordination complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each functional block autonomously determines when its processing result is ready and generates an update request signal without requiring constant external intervention. The update control unit automatically receives these signals and processes update timing decisions autonomously, reducing the need for complex manual coordination while maintaining accurate updates.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements preliminary actions by having functional blocks prepare their processing results and generate update request signals in advance before actual updates occur. The update control unit receives these preliminary signals and pre-calculates optimal update timing, avoiding the need for complex real-time coordination during the actual update process.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If update timing is synchronized across all functional blocks, then data processing accuracy improves, but processing speed decreases due to waiting for all blocks

Engineering Contradiction:
Improvedata processing accuracyVSAvoiddata processing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic update timing where the update control unit determines optimal update moments based on the actual processing status of each functional block rather than using fixed synchronous timing. The system adapts update timing dynamically to minimize waiting time while ensuring accuracy, allowing faster processing when blocks are ready without sacrificing correctness.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies partial action by updating control information only when necessary and when all relevant functional blocks are ready, rather than continuously updating or waiting for all blocks regardless of readiness. This selective updating approach reduces unnecessary waiting time while maintaining accuracy, improving overall processing speed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9519487B2System-on-chip and method of operating the same
Publication Date: 2016.12.13 SAMSUNG ELECTRONICS CO LTD
  • US9519487B2 patent drawing
  • US9519487B2 patent drawing
  • US9519487B2 patent drawing

AI summary

A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.