Arithmetic Processing Apparatus Out-of-Order Dependency Resolution
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Solution Overview
Problem
In processors that handle out-of-order execution, increasing the number of instructions that can be issued out-of-order (inflight instruction width) leads to a significant increase in the number of entries and circuit scale of the scheduler and comparator, making it difficult to improve Instruction Per Cycle (IPC) while maintaining high integration and reducing circuit scale.
Innovation Solution
An arithmetic processing apparatus with a queue and control circuitry that stores and executes multiple instructions in parallel, resolves data dependency between producer and consumer instructions, and controls the issuing timings, using pipeline stage information to optimize dependency resolution and reduce the complexity of the dependency resolution determining unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of instructions that can be issued out-of-order (inflight instruction width) is increased, then the Instruction Per Cycle (IPC) is improved, but the number of entries and circuit scale of the scheduler and comparator increase
Solution Approach 1:
The patent segments the dependency resolution function into two parts: (1) a comparator that only compares instruction identifiers to detect potential dependencies, and (2) a dependency resolution determining unit that uses pipeline stage information to resolve actual data dependencies. This segmentation allows the comparator to remain simple while enabling out-of-order execution of multiple instructions.
Solution Approach 2:
The patent adds a new dimension to dependency resolution by incorporating pipeline stage information. Instead of only comparing instruction identifiers, the system now considers the execution stage of producer instructions in the pipeline. This additional dimension allows for more efficient dependency detection without increasing comparator scale.
2Productivity
If the number of pipelines is doubled, then the parallel execution capability is improved, but the number of comparators is also doubled
Solution Approach 1:
The dependency resolution determining unit serves multiple pipelines universally by receiving pipeline stage information from any pipeline and resolving dependencies for instructions from any pipeline. This multi-functional unit eliminates the need to double comparators when adding pipelines, as the same dependency resolution logic serves all pipelines.
3Adaptability or versatility
If the number of entries in the scheduler is increased, then the out-of-order execution capability is improved, but the circuit scale increases
Solution Approach 1:
The patent uses pipeline stage information as a copy of execution state that can be stored efficiently. Instead of storing complete dependency information for each scheduler entry, the system stores compact pipeline stage indicators that can be quickly compared and used for dependency resolution, reducing the circuit scale required for each entry.
Data Source
AI summary
An arithmetic processing apparatus includes a queue and control circuitry, and executes a plurality of instructions in parallel and sequentially from executable instructions. In the arithmetic processing apparatus, the queue stores the plurality of instructions, and the control circuitry holds an indicator indicating a pipeline that executes a producer instruction included in the plurality of instructions and an execution stage of the producer instruction in the pipeline, executes data dependency resolution between the producer instruction and a consumer instruction that uses an execution result of the producer instruction and that is included in the plurality of instructions, and controls issuing timings of the plurality of instructions.