Arithmetic Processing Device Shared Storage Convolution

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Solution Overview

Problem

Conventional arithmetic processing devices require large circuit areas and high production costs due to the need for extensive storage devices to store outputs of each process layer, which increases the complexity and cost of convolutional neural networks.

Innovation Solution

The device employs a configuration with multiple storage devices and a processor that selectively reads and writes data between them, optimizing storage usage by performing convolution processes in parallel, thereby reducing the number of arrays needed for storing outputs and minimizing storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a storage device is provided for each process layer to store the entire output of the process layer, then the convolution process can be performed correctly, but the circuit area increases and production cost increases

Engineering Contradiction:

Improvecorrectness of convolution processVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the storage functions of multiple storage devices into a single shared storage device. Instead of having separate storage devices for each process layer, the invention uses one storage device that is shared across all process layers, thereby reducing the total circuit area while maintaining the ability to store and retrieve necessary data for correct convolution operations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared storage device performs multiple functions: it stores inputs for different process layers, stores intermediate results, and provides data for convolution operations across multiple layers. This multi-functional approach eliminates the need for dedicated storage devices for each layer, reducing overall circuit area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a storage device is provided for each process layer to store the entire output of the process layer, then the convolution process can be performed correctly, but the production cost increases

Engineering Contradiction:

Improvecorrectness of convolution processVSAvoidproduction cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

By merging multiple storage devices into a single shared storage device, the patent reduces the number of components that need to be manufactured and assembled. This consolidation directly lowers production costs while maintaining the functional requirements for correct convolution processing.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If multiple storage devices are used to store outputs of each process layer, then data can be stored reliably, but the device complexity increases

Engineering Contradiction:

Improvedata storage reliabilityVSAvoidnumber of storage devices

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple separate storage devices into a single shared storage device, thereby reducing device complexity. The unified storage structure simplifies the overall system architecture while maintaining data storage reliability through appropriate memory management and data organization within the shared device.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If extensive storage devices are provided to store outputs of each process layer, then the convolutional neural network can be implemented, but the circuit area and production cost increase

Engineering Contradiction:

Improvecapability to implement convolutional neural networkVSAvoidcircuit area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The shared storage device is designed to be universal, serving all process layers in the convolutional neural network. It can store and manage data for multiple layers simultaneously, providing the necessary adaptability to implement complex CNN architectures while minimizing circuit area through efficient resource sharing.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10754920B2Arithmetic processing device

Publication Date: 2020.08.25 KK TOSHIBA

AI summary

An arithmetic processing device according to the present embodiment includes: a first storage device including m (m≥2) groups each including at least one first array; a second storage device including n (m>n≥1) groups each including at least one second array; a third storage device including at least one third array; a fourth storage device including k (m>k≥1) fourth arrays; and a processor, the processor selecting n groups of the first array from among the m groups of the first array, reading out data stored in memory elements of the first array included in the selected groups, storing the data in the memory elements of the second array of the second storage device, and the processor performing a convolution process to the third array using the data stored in the memory elements of the second array and storing a result of the convolution process in the fourth arrays.