Physical Realisation TRIZ Cases
- Hardware Approximation of Activation Functions for ML Inference
Processing unit performs hardware approximation of activation functions without memory lookups.
- Neural Network Hardware Accelerator Data Parallelism via Segmented Memory Banks
Segmented memory banks eliminate sequential locking bottlenecks, allowing concurrent processor access that reduces inference latency and dark silicon usage.
- Guided Neural Network Training via Convolutional Feature Fusion
A guided training method fuses supplementary domain feature weights with convolution layer maps to balance multi-domain contributions in deep neural networks.
- Federated Learning Agent Pairing for Resilient Reporting
Paired agents superimpute results to relay updates, resolving broken link failures in federated learning.
- Neural Network Channel Optimization via Importance-Based Clipping
Processing hardware dynamically adjusts channel counts in operation branches to maintain network precision.
- Mask Attention Network for Transformer Accuracy
A mask attention network modifies original attention data structures to enhance relevance within local neighborhoods.
- Lower Triangular Matrix Allocation for Mask Attention Efficiency
Allocating operands to specific accelerator units computes only lower triangular values, eliminating unnecessary upper triangular calculations.
- Crossbar Phase Change Memory With Crystallization Seed Layer
- Heterogeneous SoC Compiler Allocating ML Inference Tasks
Compiler allocates machine learning inference tasks across heterogeneous system-on-chip cores, resolving latency and power consumption bottlenecks.
- Neural Network Graph Permutation for Sparsity
Processor permutes neural network graph data to satisfy sparsity properties, reducing memory usage and improving processing efficiency.
- Hardware Accelerated Convolution via Virtual GEMM Mapping
Virtual GEMM space mapping hardware accelerates convolution operations by directly linking matrix positions to image data structures.
- Neural Network Computing Method Reducing Memory Usage
A neural network computing method selects specific elements from previous layers to reduce memory requirements.
- Near Memory Compute Circuitry for Memory-Bound Workloads
CXL switch compute circuitry processes data near memory to resolve bandwidth and capacity trade-offs.
- Recursive Deep Learning Quantization for Weight Bit Reduction
Recursive deep learning quantization technique reduces weight storage bits by dynamically adjusting cluster counts across neural network layers.
- CNN Training Acceleration via Non-Zero Index Skipping
A convolutional neural network training method generates an index of non-zero elements during forward propagation to skip zero calculations in backward passes.
- Overpass-Type Channel Semiconductor Device for Neural Network Integration
An overpass-type channel extends effective length via a vertical fin, resolving short-channel effects to enable low-power neural network computing.
- Selective Neural Network Weight Quantization for Edge Deployment
Selective weight quantization reduces computational complexity while maintaining predictive accuracy on resource-constrained devices.
- Fusion DNN Training via Knowledge Distillation for Facial Expression Recognition
Knowledge distillation transfers features from a pre-trained teacher model to a student model, improving inference precision while reducing learning steps.
- Neural Network Robustness via Constrained Feature Encoding
An additional layer with reduced dimensionality applies n-hot encoding to constrain feature selection in neural networks.
- Serial DMA Weight Transfer for Neural Accelerator Bandwidth
Cascading weight values via serial direct memory access reduces external memory interface bottlenecks while maintaining parallel processing throughput.