Overpass-Type Channel Semiconductor Device for Neural Network Integration
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Solution Overview
Problem
Current hardware-based spiking neural networks face challenges in implementing high-accuracy and ultra-low-power computing due to the short channel effect and reduction in multi-level weights associated with high integration in synaptic devices, which limits their industrial application.
Innovation Solution
The semiconductor device incorporates an overpass-type channel structure with a fin protruding from the center of the first gate, extending the effective channel length, and a second gate with end portions extending on both sides of the fin, allowing for precise weight stabilization and low-power operation by increasing the channel length and sharing the drain voltage with the second gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high integration is implemented to increase the number of synapses and neurons, then device complexity and integration density are improved, but short channel effect occurs and the number of multi-level weights is reduced
Solution Approach 1:
The patent introduces a vertical fin structure that protrudes from the first gate, creating a three-dimensional overpass-type channel configuration. This dimensional change extends the effective channel length in the vertical direction while maintaining a compact planar footprint, thereby achieving high integration density without suffering from short channel effects that plague conventional two-dimensional channels
2Area of stationary object
If high integration is implemented to reduce device size, then area is reduced, but short channel effect and reduction in multi-level weights occur
Solution Approach 1:
By extending the channel into the vertical dimension through the fin structure, the patent achieves both miniaturization in the planar area and extended effective channel length, preserving weight precision through the overpass configuration that maintains adequate channel length despite reduced device footprint
Solution Approach 2:
The channel layer is positioned to overpass the fin structure, with the second gate wrapping around the fin from both sides. This nested configuration maximizes the use of vertical space and creates an efficient three-dimensional arrangement that achieves high integration while maintaining precise weight control
3Speed
If current is increased to improve signal transmission, then signal transmission is improved, but power consumption is increased
Solution Approach 1:
The vertical fin structure extends the effective channel length without increasing the planar area, allowing for better control of carrier transport and reduced leakage currents. This enables efficient signal transmission at lower power levels by improving the channel's ability to control current flow through the extended three-dimensional path
Data Source
AI summary
Provided is an overpass-type semiconductor device and an overpass-type semiconductor device including a channel layer that overpasses a fin of a first gate. The overpass-type semiconductor device includes: a first gate including a fin having a preset height; a charge storage layer formed on the first gate and the fin; a channel layer formed on a part of the charge storage layer; a gate insulating layer formed on the channel layer; and a second gate formed on the gate insulating layer. The fin protrudes in a height direction from a center of the first gate, and the channel overpasses the fin.