Arithmetic Processing Apparatus Transposition Buffer Circuit
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Solution Overview
Problem
Existing arithmetic processing systems face complexity and increased circuit scale when generating transposition data without breaks, particularly when using multiport memory cells, which complicates control circuits and increases area requirements.
Innovation Solution
An arithmetic processing apparatus with a single transposition buffer that successively stores and outputs data groups, utilizing a bypass route to transfer data directly to the register unit without intervention, thereby reducing circuit scale and preventing data loss during transposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiport memory cells are used to generate transposition data without breaks, then data continuity is improved, but device complexity and area requirements increase
Solution Approach 1:
A transposition buffer is introduced as an intermediary component between the memory cell array and the register unit. This buffer temporarily stores data and enables transposition operations without requiring complex multiport memory cells, thereby simplifying the control circuit while maintaining data continuity.
Solution Approach 2:
The data transfer process is segmented into distinct stages: data is first stored in the transposition buffer, then transposed, and finally transferred to the register unit. This segmentation allows each stage to be independently controlled, reducing overall system complexity while ensuring continuous data flow.
2Reliability
If multiport memory cells are used for transposition data generation, then data continuity is maintained, but the circuit area increases
Solution Approach 1:
The transposition buffer serves as a mediator that eliminates the need for area-intensive multiport memory cells. By using a standard memory cell array combined with a separate buffer, the circuit area is reduced while still achieving continuous transposition data generation.
Solution Approach 2:
Instead of achieving transposition through complex multiport access in the same spatial dimension, the solution uses a temporal dimension approach with the transposition buffer, allowing data to be stored, transposed, and transferred in sequence, thereby reducing spatial area requirements.
3Adaptability or versatility
If data is transferred through the transposition buffer, then transposition is achieved, but data loss may occur without proper control
Solution Approach 1:
Control circuits implement feedback mechanisms to monitor the transposition buffer's data transfer process. This feedback ensures that data is correctly transferred from the memory cell array to the register unit through the buffer, preventing data loss and maintaining data integrity throughout the transposition operation.
Solution Approach 2:
The control circuit performs preliminary actions by pre-configuring the transposition buffer and establishing proper data transfer protocols before the actual transposition operation begins. This preliminary setup ensures that data integrity is maintained throughout the subsequent transposition and transfer processes.
Data Source
AI summary
An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.