Array Substrate Capacitor Layout to Prevent Dielectric Cracking
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Solution Overview
Problem
Conventional capacitors in display panel backplanes face issues with abnormal display due to unstable slope angles of the first electrode, leading to dielectric portion cracking and shorts between electrodes, which reduces production yield and withstand voltage margin.
Innovation Solution
The array substrate design includes a capacitor with a first electrode, a dielectric portion, and a second electrode, where the second electrode's orthographic projection is only in the region of the first plane's projection on the base substrate, ensuring the slope angle is less than 50 degrees and avoiding shorts by terminating before the dielectric portion's slope, thus stabilizing the capacitor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the second electrode is extended to increase capacitance, then the capacitance value increases, but the slope angle increases beyond 50 degrees causing dielectric cracking
Solution Approach 1:
The patent transitions from a planar electrode design to a three-dimensional stepped structure. The second electrode includes a second plane at a first height and a third plane at a second height, creating vertical dimensionality. This stepped configuration increases the effective electrode area and capacitance while maintaining the slope angle within acceptable limits by distributing the electrode extension across multiple levels rather than a single plane.
Solution Approach 2:
The second electrode is segmented into multiple planes (second plane and third plane) at different heights. This segmentation allows the electrode to achieve increased capacitance through cumulative area while maintaining structural stability. Each plane segment contributes to the total capacitance without requiring excessive slope angles that would cause dielectric cracking.
2Quantity of substance
If the slope angle of the first electrode is increased to improve capacitance density, then the capacitance density improves, but dielectric cracking occurs reducing reliability
Solution Approach 1:
The patent uses vertical stacking with the first electrode at a first height and the second electrode having portions at different heights (first height and second height). This three-dimensional arrangement increases capacitance density by utilizing vertical space while keeping the slope angles of all electrode portions within acceptable ranges, thereby preventing dielectric cracking and maintaining reliability.
3Quantity of substance
If the second electrode area is increased to enhance capacitance, then the capacitance value increases, but shorts between electrodes occur due to improper positioning
Solution Approach 1:
The patent employs vertical separation where the first electrode is positioned at a first height and the second electrode has portions at different heights. This vertical dimensionality provides natural isolation between electrodes, allowing the second electrode to have a larger area for enhanced capacitance while maintaining proper positioning that prevents shorts through the dielectric layer.
Data Source
AI summary
The present disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a base substrate and a capacitor, the capacitor includes a first electrode, a dielectric portion and a second electrode sequentially located on the base substrate; wherein the dielectric portion includes: a first plane facing the second electrode, and a first slope surface extending from the first plane to the base substrate; and an orthographic projection, on the base substrate, of the second electrode is located in a region where an orthographic projection, on the base substrate, of the first plane of the dielectric portion is located.