Array Verification via Edge Cell Simulation
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Solution Overview
Problem
Current circuit simulation methods are inefficient due to the high computational burden of simulating each cell in an array, often relying on lumped parameter models that reduce accuracy, especially in high-speed memory designs, leading to less than ideal designs and over-specified margins, as they fail to accurately verify read and write performance across the entire array.
Innovation Solution
A computer-performed verification method that simulates only the edge cells of an array using transistor-level simulation, with center cells included for loading measurement but with internal computation disabled, and performs secondary checks on center cells and rows to ensure accurate worst-case timing analysis, reducing computational time while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full circuit simulation is performed by simultaneously modeling each cell in an array, then verification accuracy is improved, but computation time and memory requirements increase geometrically with array dimension
Solution Approach 1:
The array is segmented into edge cells and center cells. Only edge cells are fully simulated with transistor-level detail, while center cells use lumped parameter models. This segmentation allows accurate timing verification at critical edges while reducing overall computational burden by excluding center cells from detailed simulation.
Solution Approach 2:
Different simulation qualities are applied to different regions: edge cells receive high-quality transistor-level simulation with full timing analysis, while center cells use lower-quality lumped parameter models. This local quality differentiation maintains verification accuracy where it matters most (at edges) while reducing total computation time.
2Productivity
If lumped parameter models are used for inactive cells during timing analysis, then computation time is reduced, but simulation accuracy deteriorates leading to less than ideal designs and over-specified margins
Solution Approach 1:
The array is segmented into edge cells and center cells. Only edge cells are fully simulated with transistor-level detail, while center cells use lumped parameter models. This segmentation allows accurate timing verification at critical edges while reducing overall computational burden by excluding center cells from detailed simulation.
3Productivity
If all cells except edge cells are removed from the model, then computational burden is reduced to N-order, but write failures may be missed due to altered bitline and wordline loading
Solution Approach 1:
The array is segmented into edge cells and center cells. Only edge cells are fully simulated with transistor-level detail, while center cells use lumped parameter models. This segmentation allows accurate timing verification at critical edges while reducing overall computational burden by excluding center cells from detailed simulation.
Data Source
AI summary
A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.