Digital Storage TRIZ Cases
- Memory Refresh Address Generator Reducing Redundancy
Refresh address generator targets weak cells for multiple refreshes, reducing redundancy cell arrays while maintaining reliability.
- Memory Module Rank Mapping Circuit Defect Isolation
A memory module uses a rank mapping circuit to route data from defective ranks to functional ones.
- MRAM ECC Pooling for Data Reliability and Write Speed
Shared error correction blocks in MRAM reduce write latency by eliminating repeated verification cycles while maintaining data reliability.
- Magnetic Tunnel Junction Compensation Element for STRAM Scaling
A magnetic tunnel junction uses a synthetic antiferromagnetic compensation element to reduce switching current requirements.