Memory Module Rank Mapping Circuit Defect Isolation
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Solution Overview
Problem
As mobile communication terminals and sensor networks generate increasing amounts of diverse data, existing memory modules face challenges in processing big data due to defects when trying to increase capacity, leading to a need for technologies that can cope with these defects effectively.
Innovation Solution
A memory module design that includes multiple memory ranks with a rank mapping circuit to map defective ranks to defect-free ranks, blocking clock supply to defective ranks, and utilizing error correction codes and buffers to maintain functionality and capacity representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory devices is increased to achieve large capacity, then data storage capacity is improved, but the number of defects increases
Solution Approach 1:
The memory module is divided into multiple independent groups (first group and second group), each containing multiple memory ranks. This segmentation allows defective ranks in one group to be mapped to functional ranks in another group, isolating defects and maintaining overall system reliability while preserving large storage capacity.
Solution Approach 2:
A rank mapping circuit is introduced as an intermediary component that maps defective memory ranks to defect-free memory ranks across different groups. This intermediary enables the system to bypass defective components and maintain operational reliability without reducing the effective storage capacity.
2Device complexity
If defective memory ranks are maintained in the system, then device complexity is reduced, but power consumption increases due to continuous clock supply to defective ranks
Solution Approach 1:
The system dynamically controls clock signal distribution using clock gating circuits. When a memory rank is mapped to a defective rank, the clock gating circuit disables the clock signal to that defective rank, preventing unnecessary power consumption while maintaining the ability to access the mapped functional rank through the rank mapping circuit.
Solution Approach 2:
Different clock gating control strategies are applied to different groups based on their defect status. The first group may have clock gating enabled to save power on mapped ranks, while the second group maintains clock supply for functional ranks. This localized quality control optimizes power consumption without compromising overall system functionality.
Data Source
AI summary
A memory module includes: a plurality of first memory ranks that belong to a first group; a plurality of second memory ranks that belong to a second group; and a rank mapping circuit suitable for mapping a defective first memory rank among the first memory ranks to a defect-free second memory rank among the second memory ranks.