MRAM ECC Pooling for Data Reliability and Write Speed

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Solution Overview

Problem

Semiconductor memory devices, particularly MRAMs, face challenges in maintaining quick access speed while ensuring data reliability, especially when used as system or cache memory, due to limitations in error correction mechanisms.

Innovation Solution

The implementation of a memory device with a data storage region and an error correction (ECC) region, where ECC blocks are shared among data blocks, with validity, block identification, and timing information stored to facilitate efficient error correction and data management, reducing the need for repeated write-read-verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction mechanisms are implemented in MRAM devices, then data reliability is improved, but access speed deteriorates due to repeated write-read-verify operations

Engineering Contradiction:

Improvedata reliabilityVSAvoidaccess speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent performs write-verify operations in advance during the write process. The controller writes data to the MRAM device, then immediately verifies the written data by reading it back and checking for errors. This preliminary verification ensures data reliability before the data is considered fully stored, reducing the need for subsequent verification operations that would slow down access speed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The MRAM device performs self-verification of written data through integrated read circuits and error detection mechanisms. The device automatically checks the integrity of stored data without requiring external intervention, maintaining data reliability while minimizing the impact on access speed by handling verification internally and efficiently.

Inventive Principle:

Principle #25Self-service

2Reliability

If ECC blocks are dedicated to each data block, then data reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata reliabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a pooling mechanism where multiple ECC blocks form a shared pool that can serve multiple data blocks. Instead of dedicating one ECC block to each data block, the system allows any ECC block in the pool to provide error correction for any data block that needs it. This multi-functional approach maintains data reliability while reducing the total number of ECC blocks required, thereby decreasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically allocates and deallocates ECC blocks from the pool based on current needs. When a data block is successfully written and verified, its associated ECC block can be released back to the pool for reuse by other data blocks. This dynamic recovery and reuse of ECC blocks reduces the overall complexity of the error correction mechanism while maintaining reliability.

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS9552256B2Semiconductor memory device including non-volatile memory, cache memory, and computer system

Publication Date: 2017.01.24 SAMSUNG ELECTRONICS CO LTD

AI summary

In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.