Array Substrate Address Line Integration via Layered Metal Wires
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Solution Overview
Problem
The manufacturing process of array substrates in existing in-cell liquid crystal display devices is overly complex due to the need for multiple photo engraving processes for address lines and insulation layers, which complicates production.
Innovation Solution
An array substrate design where the first and second metal wires form address lines, connected through a via hole, allowing synchronous formation with scan and data lines in the same photo engraving process, simplifying the manufacturing process and avoiding additional photo engraving steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional in-cell technology is used with separate address lines and insulation layers, then the touch signal transmission function is achieved, but the manufacturing process complexity increases due to multiple photo engraving processes
Solution Approach 1:
The patent combines the address line and insulation layer into a single integrated structure. The address line is formed by connecting a first metal wire (at gate layer) and a second metal wire (at source/drain layer), eliminating the need for separate insulation layers and reducing photo engraving steps while maintaining touch signal transmission functionality.
Solution Approach 2:
The metal wire connection structure serves multiple functions: it acts as both the address line for touch signal transmission and provides inherent insulation through its layered construction. This multi-functional design eliminates the need for dedicated insulation layers, simplifying the manufacturing process.
2Manufacturing precision
If additional photo engraving processes are added for address lines, then the address line formation is achieved, but the manufacturing time and production efficiency deteriorate
Solution Approach 1:
The patent merges the address line formation process with existing photo engraving steps for scan lines and data lines. By forming address lines using the same photo engraving processes already required for other conductive elements, the total number of photo engraving steps is reduced, improving manufacturing efficiency without compromising address line precision.
Solution Approach 2:
The first and second metal wires are formed in advance during the standard TFT fabrication process, before the final assembly stages. This preliminary formation of address line components allows for integration without adding post-processing steps, maintaining manufacturing precision while improving overall production efficiency.
Data Source
AI summary
Disclosed are an array substrate and a display device which belong to the technical field of displays, and solve the technical problem that, in the existing in-cell technology, the manufacturing process of array substrates is too complex. The array substrate comprises a plurality of pixel units each having a thin film transistor, a plurality of common electrodes, and a plurality of address lines. The address lines each are formed by connecting a first metal wire and a second metal wire, the first metal wire being located at a same layer as a gate of the thin film transistor, and the second metal wire being located at a same layer as a source and a drain of the thin film transistor.