Array Substrate With Angled Transistor Active Layers
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Solution Overview
Problem
Existing array substrates face challenges in increasing the length-width ratio of transistors without expanding the pixel region, which limits high pixel design and conduction characteristics under high drive voltage.
Innovation Solution
The array substrate design includes drive transistors with active layer patterns that form a preset angle with gate lines, allowing the active layer to span the pixel region in an inclined manner, thereby increasing the length-width ratio without increasing the pixel area, and induction transistors with similarly angled active layers to enhance signal transmission accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length-width ratio of transistors is increased to improve conduction characteristics under high drive voltage, then the conduction stability is improved, but the pixel region area must be expanded which reduces pixel density
Solution Approach 1:
The active layer pattern is rotated by a preset angle (e.g., 45 degrees) relative to the gate line, changing the spatial orientation from the conventional parallel alignment. This angular reorientation allows the active layer to span across the pixel region diagonally, effectively increasing the channel length without expanding the pixel area footprint, thus resolving the contradiction between conduction stability and pixel density
2Reliability
If the active layer pattern is extended to increase the length-width ratio, then the transistor conduction characteristics are improved, but the pixel region area increases reducing high pixel design capability
Solution Approach 1:
By rotating the active layer pattern at a preset angle relative to the gate line, the channel length is extended along the diagonal direction of the pixel region. This angular transformation allows the active layer to utilize the diagonal space more efficiently, increasing the effective conduction path length without proportionally increasing the pixel area, thereby maintaining high pixel density while improving conduction characteristics
Solution Approach 2:
The active layer pattern is designed with asymmetric angular orientation (preset angle) relative to the gate line rather than symmetric parallel alignment. This asymmetric configuration optimizes the spatial utilization within the pixel region, allowing the channel to extend more effectively across the pixel area in a diagonal manner, thus achieving longer channel length with smaller area occupation
Data Source
AI summary
The present disclosure discloses an array substrate and a micro total analysis device. The array substrate includes: a substrate, a plurality of pixel regions arranged on the substrate and defined by the intersection of a plurality of data lines and a plurality of gate lines, and a plurality of drive transistors arranged in the plurality of pixel regions respectively; each drive transistor includes a first active layer pattern, a first extension direction of the first active layer pattern forms a first preset angle with a gate line, and in a first preset angle direction, the first active layer pattern spans a pixel region in an inclined manner; and source and drain electrodes of the each drive transistor are coupled with the active layer pattern in the first preset angle direction.