Array Substrate Bridge Pattern for Connection Integrity
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Solution Overview
Problem
The existing array substrates for GIP structure display devices face disconnection issues in the connection pattern due to undercut structures in the gate insulating layer and passivation layer, leading to electrical disconnectivity between the gate and source-drain layers.
Innovation Solution
The implementation of a bridge pattern on a planarization layer with larger pack holes corresponding to contact holes, which overlaps the auxiliary patterns and provides a flat surface, preventing disconnection by filling the undercut structures and ensuring electrical connectivity between the gate and source-drain layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a connection pattern is formed directly on the passivation layer to connect auxiliary patterns, then the fabrication process is simplified, but undercut structures in the gate insulating layer and passivation layer cause disconnection in the connection pattern
Solution Approach 1:
The patent introduces a bridge pattern as an intermediary element between the connection pattern and the auxiliary patterns. The bridge pattern is formed on the planarization layer and extends into the contact holes, providing a reliable connection path that bridges the gap caused by undercut structures. This mediator ensures electrical connectivity without requiring changes to the overall fabrication process complexity.
Solution Approach 2:
The patent adds a vertical dimension to the connection structure by forming the bridge pattern that extends downward into the contact holes through the passivation layer. Instead of relying solely on a horizontal connection pattern on the passivation layer surface, the solution creates a three-dimensional connection path that reaches the auxiliary patterns at different depth levels, thereby overcoming the disconnection issue caused by undercut structures.
2Ease of manufacture
If the gate insulating layer and passivation layer are formed with standard thickness, then the fabrication process is straightforward, but undercut structures occur at the contact holes leading to connection failure
Solution Approach 1:
The patent segments the connection structure into multiple functional parts: the connection pattern on the passivation layer surface, the bridge pattern extending into the contact holes, and the planarization layer providing a flat base. This segmentation allows each component to perform its specific function - the bridge pattern specifically addresses the undercut issue by providing a vertical connection path, while the other layers maintain their standard fabrication processes.
Data Source
AI summary
A method of fabricating an array substrate, forming a gate line in a display region and a first auxiliary pattern in a non-display region forming a gate insulating layer on the gate line and the first auxiliary pattern forming a data line in the display region and a second auxiliary pattern in the non-display region over the gate insulating layer, wherein the data line crosses the gate line to define a pixel region forming a passivation layer on the data line and the second auxiliary pattern, and the passivation layer including first and second contact holes respectively exposing the first and second auxiliary patterns forming a planarization layer and a bridge pattern on the passivation layer forming a pixel electrode on the planarization layer and in the pixel region, and a connection pattern on the bridge pattern, wherein the connection pattern contacts the first and second auxiliary patterns.