Top-Gate Array Substrate Layout for Lower Data Line Capacitance
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Solution Overview
Problem
Existing display apparatus with top gate structure have a large number of light shielding layers, leading to higher costs and a limited application range due to increased power consumption and reduced performance.
Innovation Solution
The array substrate includes an underlay substrate with at least one first transistor, data line, and pixel electrode. The first transistor has a first active layer and a first gate, with the gate located on a side away from the underlay substrate, and the data line is positioned close to the underlay substrate to reduce capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the data line is positioned close to the underlay substrate, then the capacitance between the data line and the pixel electrode is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent positions the data line in the horizontal plane close to the underlay substrate, while the pixel electrode is positioned in the vertical direction above the active layer. This spatial separation in different dimensions reduces the capacitance between the data line and pixel electrode, thereby reducing power consumption while maintaining manufacturability through standardized layer stacking processes.
2Object-affected harmful factors
If multiple light shielding layers are added to the top gate structure, then the light shielding performance is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the light shielding function from the traditional top gate structure by positioning the data line close to the underlay substrate. This spatial reconfiguration inherently reduces light interference pathways while eliminating the need for multiple light shielding layers, thereby simplifying the overall device structure and reducing manufacturing complexity.
Data Source
AI summary
An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.