Array Substrate Capacitor Line Shielding for LCD Aperture Ratio

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Solution Overview

Problem

The aperture ratio of liquid crystal display (LCD) devices is reduced due to the need to maintain a distance between the pixel electrode and the data line to avoid parasitic capacitance and the requirement for a wide black matrix to cover substrate misalignment, which hinders the improvement of display brightness.

Innovation Solution

The design includes a substrate with a data line, passivation layer, gate line, gate insulation layer, semiconductor layer, contact holes, and electrodes formed using transparent conductive materials like indium tin oxide (ITO) or indium zinc oxide (IZO), where the capacitor line width is wider than the data line, allowing for a narrower pixel electrode width and improved coverage by the black matrix.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the distance between the pixel electrode and the data line is increased to avoid parasitic capacitance, then the parasitic capacitance is reduced, but the aperture ratio is reduced

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

A capacitor line is introduced as an intermediary element between the data line and the pixel electrode. This capacitor line is overlapped with the data line and connected to ground through a contact hole, acting as a shield to reduce parasitic capacitance between the data line and pixel electrode without requiring increased spacing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution transitions from a planar arrangement (spacing in one dimension) to a three-dimensional arrangement by overlapping the capacitor line with the data line in the vertical dimension. This allows parasitic capacitance reduction through vertical stacking rather than horizontal spacing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a wide black matrix is used to cover substrate misalignment, then the misalignment coverage is improved, but the aperture ratio is reduced

Engineering Contradiction:
Improvemisalignment coverageVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The black matrix is merged with the capacitor line structure, where the capacitor line is positioned within or integrated with the black matrix region. This allows the black matrix to serve dual functions: covering misalignment and providing the capacitor line for parasitic capacitance reduction, thereby reducing the required width of the black matrix.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If the pixel electrode width is reduced to increase aperture ratio, then the aperture ratio is improved, but the manufacturing precision requirement is increased

Engineering Contradiction:
Improveaperture ratioVSAvoidpixel electrode width control
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The capacitor line acts as a mediator that provides parasitic capacitance reduction without requiring precise control of pixel electrode dimensions. By placing the capacitor line overlapped with the data line and connecting it to ground, the system achieves electrical isolation without relying on tight tolerances for pixel electrode positioning or sizing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7705360B2Array substrate for display device and method of manufacturing the same
Publication Date: 2010.04.27 LONESTAR CRYSTAL DISPLAY LLC
  • US7705360B2 patent drawing
  • US7705360B2 patent drawing
  • US7705360B2 patent drawing

AI summary

An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.