Array Substrate Multi-Layer Common Electrode Aperture Ratio
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Solution Overview
Problem
Liquid crystal displays have a low aperture ratio due to common electrode lines and gate lines being arranged in the same layer, resulting in spaces that hinder image display and reduce light transmission efficiency.
Innovation Solution
The array substrate design includes multiple metal layers with common electrode lines connected through via holes, reducing planar distances between these lines and other signal lines, and featuring a networked structure to enhance aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If common electrode lines and gate lines are arranged in the same layer, then the device complexity is reduced, but the aperture ratio decreases due to spaces required between lines
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar arrangement to a three-dimensional stacked arrangement. Common electrode lines are distributed across multiple metal layers (first metal layer, second metal layer, third metal layer) stacked in the vertical direction, connected through via holes. This spatial reorganization eliminates the need for lateral spacing between common electrode lines and gate lines, thereby increasing the aperture ratio while maintaining electrical connectivity.
2Area of moving object
If common electrode lines are placed in multiple metal layers, then the aperture ratio increases, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the common electrode lines into multiple segments located in different metal layers. Each metal layer contains portions of the common electrode lines, and these segments are electrically connected through via holes that penetrate the insulating layers between metal layers. This segmentation allows for increased aperture ratio while managing manufacturing complexity through systematic layer-by-layer construction.
3Reliability
If spaces are maintained between common electrode lines and gate lines, then electrical insulation is ensured, but the aperture ratio decreases
Solution Approach 1:
The patent resolves the insulation issue by utilizing the vertical dimension. Common electrode lines in different metal layers are electrically isolated by insulating layers (first insulating layer, second insulating layer) positioned between the metal layers. This three-dimensional arrangement allows common electrode lines to be in close proximity or even overlap in the planar view while maintaining electrical insulation through the vertical stacking, thereby maximizing aperture ratio without compromising insulation reliability.
Data Source
AI summary
An array substrate, a manufacture method thereof and a display device are provided. The array substrate includes a base, and multiple metal layers configured to be insulated from each other and arranged on the base, each of at least two metal layers of the multiple metal layers includes a common electrode line and the common electrode lines in the at least two metal layers are connected to each other.