Array Substrate Common Electrode Hollowed-Out Design
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Solution Overview
Problem
In display technology, the overlap between the common electrode and the active layer of thin film transistors leads to reduced electron mobility and stability of the threshold voltage, causing performance issues in display panels.
Innovation Solution
The array substrate design incorporates a first hollowed-out portion in the common electrode that covers the channel region of the thin film transistor, reducing parasitic capacitance and improving electron mobility, with additional via holes and layers ensuring electrical connectivity without overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the common electrode overlaps with the active layer of the thin film transistor, then the electrical connectivity is ensured, but the electron mobility is reduced and the threshold voltage stability deteriorates due to increased parasitic capacitance
Solution Approach 1:
The patent extracts the harmful overlapping region between the common electrode and the active layer by creating a hollowed-out portion in the common electrode that removes material directly above the channel region. This extraction eliminates the parasitic capacitance formed by the overlap while maintaining electrical connectivity through via holes that pass through the hollowed-out region to connect lower conductive layers.
Solution Approach 2:
The common electrode is segmented into multiple regions: a hollowed-out portion above the channel region to reduce parasitic capacitance, and connected regions through via holes to maintain electrical connectivity. This segmentation allows different portions of the common electrode to serve different functions - isolation over the channel and connectivity through the via holes to source/drain regions.
2Speed
If the common electrode is designed with a hollowed-out portion to reduce parasitic capacitance, then the electron mobility is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent adds a vertical dimension to the common electrode structure by creating via holes that extend downward from the hollowed-out portion. This dimensional change allows the electrode to maintain connectivity to lower layers while being hollowed out in the horizontal plane above the channel, effectively resolving the contradiction between reducing parasitic capacitance and maintaining electrical connectivity.
3Object-affected harmful factors
If the hollowed-out portion of the common electrode covers the channel region, then the parasitic capacitance is reduced, but the area of the common electrode is decreased
Solution Approach 1:
The patent selectively extracts material from the common electrode only in the region directly above the channel, creating a hollowed-out portion that reduces parasitic capacitance. The via holes then provide alternative pathways for electrical connectivity, ensuring that the overall functionality is maintained despite the reduced electrode area in the critical region.
Data Source
AI summary
An array substrate and a manufacturing method thereof, and display panel are disclosed. The array substrate includes a substrate, a thin film transistor disposed on the substrate and a common electrode disposed on a side of the thin film transistor away from the substrate. The common electrode includes a first hollowed-out portion. An active layer of the thin film transistor includes a source electrode region, a drain electrode region and a channel region. An orthographic projection of the first hollowed-out portion on the substrate at least covers an orthographic projection of the channel region on the substrate.