Array Substrate Common Electrode Signal Line Via Hole Connection
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Solution Overview
Problem
In liquid crystal displays with a dual-gate structure, capacitive coupling leads to uneven luminance between adjacent sub-pixel columns with positive and negative voltage polarities, causing vertical bright and dark streaks, which existing technologies attempt to address with additional metal layers that complicate the manufacturing process.
Innovation Solution
An array substrate with a Z1 structure is developed, featuring a gate layer, insulating layers, a source-drain layer, and a common electrode layer, where common electrode signal lines are integrated within the same layer as data lines and sources, drains, and via holes connect these lines to the common electrode layer, reducing manufacturing complexity and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dual-gate structure is used to achieve high pixel definition, then pixel definition is improved, but vertical lines appear due to capacitive coupling causing uneven luminance
Solution Approach 1:
The patent extracts the common electrode signal line from the traditional structure and creates a dedicated connection path through via holes to the common electrode layer. This separation allows independent control of the common electrode potential, eliminating the capacitive coupling effect that causes vertical lines while maintaining the dual-gate structure's high pixel definition.
Solution Approach 2:
The patent introduces via holes as intermediary connection elements between the common electrode signal line and the common electrode layer. These via holes serve as conductive mediators that directly connect the signal line to the common electrode, providing a low-impedance path that stabilizes the common electrode potential and prevents luminance unevenness.
2Object-affected harmful factors
If additional metal layers are added to address vertical lines, then vertical lines are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent makes the source-drain layer multi-functional by integrating both data line and common electrode signal line functions into the same layer. This universal design eliminates the need for additional dedicated metal layers for common electrode connections, reducing manufacturing complexity while effectively addressing vertical lines through the via hole connection mechanism.
Solution Approach 2:
The patent merges the common electrode signal line with the data line in the same source-drain layer, combining two previously separate functions into one integrated structure. This merging reduces the total number of manufacturing steps and material layers required, simplifying the overall manufacturing process while maintaining effective vertical line suppression.
3Ease of manufacture
If common electrode signal lines are placed in the same layer as data lines, then manufacturing process is simplified, but signal interference may increase
Solution Approach 1:
The patent segments the common electrode signal line into multiple separate line segments within the source-drain layer, with each segment connected to the common electrode layer through individual via holes. This segmentation distributes the signal path and reduces current density, minimizing signal interference while maintaining the manufacturing simplicity of using a single layer for both data and common electrode signals.
Data Source
AI summary
An array substrate includes a gate layer, a first insulating layer, a channel layer, a source-drain layer, a second insulating layer, and a common electrode layer that are sequentially stacked, wherein the second insulating lay is provided with via holes formed therein; and the source-drain layer includes a plurality of sources, a plurality of drains, a plurality of data lines and a plurality of common electrode signal lines. The common electrode signal line includes a plurality of common electrode signal line segments, each of the common electrode signal line segments passes through at least one sub-pixel row, and each of the common electrode signal line segments is connected to the common electrode layer through the via hole.