Array Substrate Common Hole Design for Panel Stain Reduction
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Solution Overview
Problem
In liquid crystal display technology, the deep section drop of common holes and connection holes leads to poor diffusion of PI or metal solutions, resulting in panel stains during the assembly of cells, particularly in both bottom-gate and top-gate array substrates.
Innovation Solution
A method of manufacturing an array substrate that reduces the section drop of common holes by forming a first connection portion from the same material as the second electrically conductive layer within the holes, ensuring electrical contact and maintaining the same thickness as the second conductive layer, thereby alleviating poor diffusion issues and panel stains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If common holes are formed deep through multiple layers (gate insulating layer, etch barrier layer, passivation layer), then electrical connection is achieved, but section drop increases causing poor PI solution diffusion and panel stains
Solution Approach 1:
The common hole is divided into two segments: an upper portion and a lower portion with different depths. The first connection portion is formed only in the upper portion at a shallower depth, avoiding the need to penetrate through all layers. This segmentation reduces section drop while maintaining electrical connection functionality.
Solution Approach 2:
The connection structure transitions from a single vertical through-hole to a multi-level structure with connection portions at different depths. The first connection portion is positioned at a shallower depth level, creating a stepped configuration that reduces the effective hole depth for PI solution diffusion while preserving electrical connectivity.
2Reliability
If connection holes are formed to connect source/drain electrodes, then electrical connectivity is established, but section drop causes poor metal solution diffusion and panel stains
Solution Approach 1:
The connection hole structure is segmented into different depth portions. The first connection portion is formed only in the upper portion at a controlled shallower depth, separating the electrical connection function from the need to penetrate the entire layer stack. This reduces section drop and improves metal solution diffusion uniformity.
3Manufacturing precision
If additional processes are added to improve PI solution coating, then diffusion uniformity may improve, but manufacturing complexity and cost increase
Solution Approach 1:
The first connection portion is formed in advance during the same sputtering process that creates the second electrically conductive layer. This preliminary formation of the connection portion eliminates the need for separate coating improvement processes, reducing manufacturing complexity while achieving the desired diffusion uniformity through the reduced section drop geometry.
Data Source
AI summary
There is disclosed a method of manufacturing an array substrate, the method including a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors on the substrate includes: forming a first electrically conductive layer on the substrate; forming an insulating layer on the first electrically conductive layer; forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer; forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer. In addition, there is disclosed an array substrate manufactured by the above method and a display device including the array substrate.