Array Substrate Conductive Strips for Electrostatic Discharge
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Solution Overview
Problem
Electrostatic discharging during the dry etching process for forming the active layer pattern of the TFT channel region can burn down the data shorting bar and lead to a short circuit between the data metal layer and the gate metal layer, significantly reducing the production yield rate of array substrates.
Innovation Solution
The array substrate design includes a first data shorting bar on the gate metal layer and a second data shorting bar on the data metal layer, with a first conductive strip coupled to the first data shorting bar and a second conductive strip coupled to the second data shorting bar, where the width of the conductive strips is greater than the respective data shorting bars, increasing overlapped capacitance and scattering electrostatic charges to reduce electric potential differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data metal layer pattern carries electrostatic charges during the dry etching process, then the electrostatic charges aggregate at different positions on the data line creating different electric potentials, but this leads to electrostatic discharging that may burn down the data shorting bar and cause short circuit between data metal layer and gate metal layer
Solution Approach 1:
The patent introduces a shorting bar structure that connects different potential regions of the data line, creating an equipotential path. This allows electrostatic charges to distribute uniformly across the shorting bar, reducing potential differences and preventing electrostatic discharge that would otherwise damage the data shorting bar or cause short circuits between metal layers.
Solution Approach 2:
The patent introduces a gate insulation layer as an intermediary between the data metal layer and gate metal layer. This intermediate layer prevents direct contact and potential short circuiting between the two metal layers, while still allowing the electrostatic charges to be managed through the shorting bar structure on the data line itself.
2Reliability
If the intensity of the electric field on the gate insulation layer increases due to continuous aggregation of electrostatic charges, then the electric field may break down the gate insulation layer, but this causes short circuit between data metal layer and gate metal layer
Solution Approach 1:
By creating an equipotential region through the shorting bar, the patent reduces the electric field intensity across the gate insulation layer. When charges are distributed uniformly at the same potential, the electric field strength decreases, preventing breakdown of the insulation layer and avoiding short circuits between metal layers.
Solution Approach 2:
The shorting bar structure is designed in advance to provide a charge distribution mechanism before electrostatic discharge can occur. This preventive structure cushions against potential electric field breakdown by managing charge accumulation proactively during the etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the intensity of the electric field on the gate insulation layer, preventing electrostatic discharging that could burn down the data shorting bar or cause a short circuit, thereby improving the production yield rate of array substrates.
Implementation Method 1
the width of the conductive strips is greater than the respective data shorting bars, increasing overlapped capacitance and scattering electrostatic charges to reduce electric potential differences
Implementation Method 2
the data metal layer pattern carries electrostatic charges, the electrostatic charges aggregated at different positions on the data line are in different electric potentials
Implementation Method 3
the intensity of the electric field generated on the gate insulation layer at the overlap between the data metal layer pattern and the gate metal layer pattern
Data Source
AI summary
According to one aspect of the present invention, the provided is an array substrate. Specifically, the first conductive strip that is coupled to the first data shorting bar and the second conductive strip that is coupled to the second data shorting bar are formed on the array substrate. The width of the first conductive strip is greater than the width of the first data shorting bar. The width of the second conductive strip is greater than the width of the second data shorting bar. The first conductive strip is overlapped with the second conductive strip. Such a structure of the array substrate effectively increases the overlapped capacitance between the data metal layer and the gate metal layer.