Array Substrate Connection Line Resistivity Management
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Solution Overview
Problem
Existing display technologies face issues with connection line burnout due to high resistivity materials used for gate lines, leading to abnormality in display panels when large currents are applied, causing heating and potential burnout.
Innovation Solution
The array substrate design features connection lines with lower resistivity than gate lines, made of the same material, and includes thin film transistors and connection strips to manage current flow, reducing heating power and preventing burnout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines are made with high resistivity materials to reduce interference and improve signal integrity, then signal quality is improved, but connection lines experience excessive heating and potential burnout when transmitting large currents
Solution Approach 1:
The patent applies different resistivity characteristics to different parts of the wiring system: gate lines use higher resistivity materials to minimize interference and improve signal integrity, while connection lines use lower resistivity materials to reduce heating during high current transmission. This local differentiation resolves the contradiction by optimizing each component's material properties for its specific functional requirements.
Solution Approach 2:
The patent changes the resistivity parameter of connection line materials to be lower than that of gate lines. By adjusting this physical parameter, the connection lines can handle large currents without excessive heating, while gate lines maintain their higher resistivity for better signal integrity. This parameter optimization resolves the contradiction between signal quality and thermal management.
2Ease of manufacture
If connection lines use the same material as gate lines for manufacturing simplicity, then manufacturing complexity is reduced, but connection lines suffer from burnout under high current conditions
Solution Approach 1:
The patent differentiates material selection between connection lines and gate lines based on their functional requirements. Connection lines use lower resistivity materials to withstand high currents, while gate lines use higher resistivity materials for signal integrity. This local quality differentiation maintains manufacturing simplicity while significantly improving connection line durability under high current conditions.
3Reliability
If process complexity is increased to implement different materials for connection lines and gate lines, then connection line reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes the resistivity parameter of connection line materials to be lower than gate line materials, which can be achieved through standard semiconductor manufacturing processes. This parameter change improves connection line reliability without requiring fundamentally new manufacturing techniques, thus limiting the increase in manufacturing complexity while achieving the reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the risk of connection line burnout by lowering heating power during high current transmission, ensuring stable display performance.
Implementation Method 1
A resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line
Data Source
AI summary
An array substrate includes: a base substrate; at least one first connection terminal, at least one second connection terminal, and at least one connection line, which are disposed on the base substrate and located in a non-display area of the array substrate, the at least one connection line being connected with the at least one first connection terminal and the at least one second connection terminal; at least one gate line disposed on the base substrate and located in a display area of the array substrate. The first connection terminal is for connecting with an IC, and the second connection terminal is for connecting with a flexible circuit board. A resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line.