Array Substrate Data Line Branching for Capacitance Reduction
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Solution Overview
Problem
In liquid crystal display technology, the coupling capacitance at the overlapping region between gate and data lines adversely affects signal transmission, deteriorating display quality, especially as display panel size increases.
Innovation Solution
The array substrate design includes data lines divided into first and second branches at the intersection with gate lines, where the first branch overlaps the gate line with a reduced width, and the second branch overlaps the gate electrode of a TFT, with a thinning and widening portion to minimize the overlapping area and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the data line and gate line are designed with standard width for simple manufacturing, then the manufacturing process is simple, but the coupling capacitance at the overlapping region increases and deteriorates display quality
Solution Approach 1:
The patent applies local quality by making the data line width variable: the first branch (overlapping the gate line) has a reduced width to minimize coupling capacitance, while the second branch (non-overlapping) maintains standard width for normal signal transmission. This local differentiation resolves the contradiction by reducing capacitance only where needed without compromising overall manufacturing simplicity.
Solution Approach 2:
The data line is segmented into two distinct branches: the first branch with reduced width for the overlapping region, and the second branch with standard width for non-overlapping regions. This segmentation allows each portion to be optimized for its specific function, reducing coupling capacitance in the critical overlapping area while maintaining standard dimensions elsewhere.
2Object-affected harmful factors
If the data line width is reduced at the overlapping region to reduce coupling capacitance, then the coupling capacitance decreases and display quality improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the width parameter of the data line from a constant value to a variable value with two distinct widths. The first branch uses a reduced width parameter to minimize coupling capacitance, while the second branch uses the standard width parameter. This parameter change approach allows optimization of capacitance without requiring continuous precision control, as only discrete width values are needed.
Data Source
AI summary
The present disclosure provides an array substrate and a display device. The array substrate includes gate lines, data lines, and thin film transistors (TFTs) connected to the gate lines and the data lines. At least one of the data lines is divided into a first branch and a second branch at a predetermined region where an intersection of the at least one of the data lines and at least one of the gate lines is located. The first branch overlaps the at least one of the gate lines, and has a width less than a width of a non-overlapping portion of the at least one of the data lines which does not overlap the at least one of the gate lines. The second branch overlaps a gate electrode of a corresponding one of the TFTs, and serves as, or is connected to, a source electrode of the corresponding TFT.