Solid-State Devices TRIZ Cases

Forming a metal silicide layer as buried bit lines reduces resistance and prevents junction leakage caused by voids in CVD tungsten deposition.

A fingerprint sensor adjusts reference voltages per vertical line to optimize sensing sensitivity across the display array.

Plasma-activated bonding stacks capacitor-less DRAM cells above logic devices, resolving substrate size constraints while preventing thermal damage.

Selective cap layer etching defines distinct transistor gates for split-gate memory cells and peripheral devices on a shared substrate.

Segmenting the first electrode into emission and non-emission areas creates pathways for trapped gas to escape from the passivation layer.

Sequentially expanding inorganic layers cover organic layer edges to block moisture penetration while preventing interlayer lifting.

Replacing cobalt with iron alloys in the free layer reduces damping and lowers switching current while maintaining perpendicular magnetic anisotropy.

A contactless user interface device uses organic semiconductor photon sensors to detect shadow variations for position and distance tracking.

An inorganic pattern layer with protrusions reduces external light reflection while maintaining image brightness.

A temporary fixing film composed of a high molecular weight component and silicone-modified resin provides controlled adhesion for semiconductor wafers.

Amorphous fluoropolymer reinforces OLED light-emitting layers against solvent corrosion during electron transport layer formation.

Epitaxial silicon growth on sacrificial fins doubles device density while resolving fin spacing control limitations.

Gate contact recesses in the AlGaN barrier layer match threshold voltages of enhancement and depletion mode devices, reducing output capacitance.

A photoreceptor protein-based spectrophotometer converts absorbed light into electrical signals using field-effect transistors.

Sealed cavity structures under shallow trench isolation reduce substrate coupling, enabling high linearity on cost-effective bulk silicon wafers.

A unit pixel capacitor uses protruding wiring patterns to increase electrode surface area and capacitance.

High-k metal gate transistor lowers threshold voltage for additional writing, eliminating complex peripheral circuits and reducing resistance variations.

A resetting method for resistive random access memory cells using adaptive voltage levels to verify and heal resistance states.

Asymmetric L-shaped heater structures redirect heat flow away from adjacent cells, mitigating thermal disturbance during programming operations.

A multilevel memory stack structure uses sacrificial fill material to form inter-stack openings for vertical NAND strings.

Dynamic MOS coupling prevents short circuits during normal operation while providing low-resistance paths to dissipate ESD events between negative supply rails.

Counter-doped back-gates in SOI transistors enable dynamic performance modulation, resolving the trade-off between switching speed and leakage current.

Graded phosphorescent concentration profiles within segmented OLED emissive layers mitigate electron-induced degradation and extend operational lifetime.

A light emitting element configuration with segmented insulating films and through-holes enables separate electrical property checks for each series-connected cell.

An oxide barrier layer prevents metal diffusion from the reflective layer, reducing light-emitting element defects while maintaining reflectivity.

Replacing low conductivity M2 glue with high thermal conductivity paste reduces resistance below 7 K/W while maintaining manufacturing simplicity.

An insulating film segments the space between source and back gate regions to suppress parasitic bipolar transistor operation.

Langmuir-Blodgett assembly of silver nanowire monolayers creates SERS substrates that overcome the difficulty of ordering non-spherical nanostructures.

Adhesion enhancement pattern under insulation film prevents rolling and passivation cracks, blocking moisture intrusion paths.

A segmented column spacer with a recessed sub spacer disperses stress to prevent deformation while increasing the liquid crystal injection margin.

Segmented gates and a charge storage layer enable dual programming in non-volatile memory cells, resolving the trade-off between density and speed.

Patterned film between wires acts as repair line, reducing capacitance and signal rounding in display devices.

Segmented buffer layers in a nanocomposite photodetector block electron and hole conduction, reducing dark current while maintaining high UV responsivity.

Stepwise graded refractive index film layers reduce total internal reflection at interfaces, increasing external quantum efficiency in OLED displays.

Stacking segmented phosphor layers in a conversion film resolves the trade-off between light extraction and conversion efficiency.

A display device uses a buffer layer with a gentler step in the transistor area to stabilize the insulating layer and prevent cracking.

A solid-state imaging apparatus uses variable aperture areas in a light shielding layer to equalize pixel sensitivity across different photoelectric conversion element sizes.

A light guide structure redirects emission between subpixel areas to enable independent color control without fine metal masks.

Refractive optics redirect wiring area light to hide circuitry, resolving the trade-off between gate driver integration and border width.

Buried conduction lines eliminate separate current control contacts, resolving the contradiction between precise current sensing and increased chip size.

Merging assist gates reduces pitch between fin-type stacked structures, resolving integration density limits while maintaining reliability.

A bridging element with nonlinear electrical resistance protects optoelectronic semiconductor chips from overvoltages.