Dual-Function Non-Volatile Memory Cell With Segmented Gates
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Solution Overview
Problem
Existing non-volatile semiconductor memory cells are slow and inefficient, particularly in achieving both one-time and multi-time programming functions within a simpler structure.
Innovation Solution
A non-volatile semiconductor memory cell with dual functions is designed, featuring a substrate with multiple gates and diffusion regions, where specific voltage configurations allow for both one-time and multi-time programming functions, utilizing a charge storage layer between the gates to facilitate efficient programming and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage structures are utilized to form 2-bit non-volatile semiconductor memory transistors, then memory cell density is improved, but programming speed and efficiency deteriorate
Solution Approach 1:
The memory cell is segmented into distinct functional regions with separate gates: a first gate for selecting the memory cell, and a second gate for programming operations. This segmentation allows independent optimization of selection and programming functions, enabling faster programming speeds while maintaining high density through the charge storage layer structure.
Solution Approach 2:
The invention introduces a vertical charge storage layer between the first and second gates, transitioning from a planar memory structure to a three-dimensional configuration. This dimensional change increases storage capacity per unit area while the separated gate structure maintains programming efficiency by allowing direct voltage application to the charge storage layer.
2Adaptability or versatility
If complex fabrication steps are used to achieve dual programming functions, then functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The memory cell structure is designed with universal components that serve multiple functions: the charge storage layer can store charges for both one-time programming (OTP) and multi-time programming (MTP), while the first and second gates can be configured to perform different programming operations. This multi-functionality is achieved through a single fabrication process, reducing overall manufacturing complexity.
Solution Approach 2:
The invention achieves dual programming functions by changing voltage parameters applied to the gates rather than requiring structurally different memory cells. By applying specific voltage combinations to the first and second gates, the same physical structure can perform both OTP and MTP operations, simplifying the fabrication process while maintaining functional versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory cell achieves improved performance by enabling efficient one-time and multi-time programming functions within a simpler structure, enhancing memory cell density and operational efficiency compared to prior art.
Implementation Method 1
a charge storage layer filled between the second gate and the third gate
Implementation Method 2
an oxide layer below the second gate and the third gate ruptured with the first voltage wherein the select-gate voltage is half the first voltage
Data Source
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AI summary
A non-volatile semiconductor memory cell (300) with dual functions includes a substrate, a first gate (313-1), a second gate (313-2), a third gate (313-3), a charge storage layer (314), a first diffusion region (311-1), a second diffusion region (311-2), and a third diffusion region (311-3). The second gate (313-2) and the third gate (313-3) are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region (311-1) is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region (311-2) is used for receiving a fifth voltage corresponding to the multi-time programming function.