Integrated Circuit Memory With High-k Metal Gate Transistor
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Solution Overview
Problem
Existing memory systems for programmable logic switches in FPGAs face variations in writing results due to the need for additional circuits to manage voltage and current, leading to complex memory peripheral circuit configurations.
Innovation Solution
The use of transistors with high-k metal gates, which allow for repeated writing and erasing operations by adjusting threshold voltages and current levels, simplifying the circuit configuration and reducing variations in memory device resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional writing is performed to prevent or reduce variation in memory writing results, then writing reliability is improved, but device complexity increases due to additional circuits
Solution Approach 1:
The memory device performs additional writing operations autonomously without requiring external control circuits. The write circuit detects writing status and automatically executes additional writing when needed, making the system self-regulating and eliminating the need for complex peripheral circuits to manage additional writing operations.
Solution Approach 2:
The invention changes the writing parameters (voltage levels, pulse widths) dynamically based on the detected writing status and memory cell state. By adjusting these parameters, the system achieves reliable additional writing without requiring additional hardware circuits, thus improving reliability while maintaining simple circuit configuration.
2Manufacturing precision
If transistors with high-k metal gates are used to enable repeated writing and erasing operations, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The write circuit is designed to perform multiple functions: initial writing, additional writing, erasing, and status detection, all using the same high-k metal gate transistor structure. This multi-functional approach achieves precise control of memory device resistance states without requiring separate specialized circuits for each operation, thereby improving manufacturing precision while avoiding increased device complexity.
3Reliability
If additional circuits are added to manage voltage and current for flash-memory devices, then writing reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The invention merges the functions of voltage management, current control, writing operation, erasing operation, and status detection into a single integrated write circuit. This consolidation achieves reliable writing results through coordinated control of voltage and current while simplifying the overall circuit configuration, making the memory device easier to manufacture without requiring multiple separate control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and reliable memory operations with reduced complexity in circuit design, allowing for effective additional writing and initialization without the need for additional circuits, thereby minimizing variations in memory device performance.
Implementation Method 1
a first transistor including a high-k metal gate, one of a source and a drain of the first transistor being connected to the first wiring line
Implementation Method 2
a third circuit configured to lower a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value
Data Source
AI summary
An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.