Multilevel Memory Stack Fabrication via Sacrificial Fill Removal
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming monolithic vertical NAND string memory devices with multiple levels, as existing methods struggle to achieve high density and scalability while maintaining effective charge storage and retention.
Innovation Solution
The method involves forming a vertical stack of multilevel memory arrays by alternating stacks of insulating and sacrificial material layers, followed by selective etching and deposition of conductive materials, creating stepped surfaces and memory openings, and replacing sacrificial layers with conductive electrodes, allowing for the formation of monolithic three-dimensional NAND string memory devices with improved density and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods are used to form three-dimensional memory devices, then device structure is simpler, but manufacturing precision and scalability are insufficient for high-density multilevel memory
Solution Approach 1:
The memory device is divided into multiple levels (first level, second level, third level) with distinct memory openings, sacrificial material layers, and conductive electrode structures at each level. This segmentation enables precise control of manufacturing processes for each level while achieving high-density three-dimensional memory through vertical stacking of multiple independently formed levels
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to vertical three-dimensional structures by stacking multiple memory levels above a substrate. Memory openings extend through alternating insulating and sacrificial material layers in the vertical dimension, enabling high-density storage through z-axis expansion rather than lateral scaling
2Quantity of substance
If multilevel memory structures are formed, then storage density increases, but charge storage and retention effectiveness becomes difficult to maintain
Solution Approach 1:
Sacrificial material layers are deposited between insulating layers and serve as temporary intermediaries during fabrication. These sacrificial layers are subsequently removed to form cavities that are filled with conductive electrode materials, enabling precise formation of multilevel memory structures with proper charge storage characteristics at each level
Solution Approach 2:
The patent employs selective etching processes that remove sacrificial material layers while preserving insulating layers and previously formed structures. This parameter-based selectivity enables precise control of material removal and deposition processes, maintaining charge storage reliability through controlled formation of memory openings and electrode structures at multiple levels
3Productivity
If conventional fabrication methods are used, then manufacturing process is simpler, but productivity and scalability for high-density memory are insufficient
Solution Approach 1:
Alternating stacks of insulating and sacrificial material layers are formed in advance before memory openings are etched. This preliminary formation of layered structures enables subsequent selective removal of sacrificial materials and efficient filling of memory openings with conductive electrodes, improving overall manufacturing productivity through pre-planned process sequencing
Solution Approach 2:
Multiple memory levels are nested vertically above the substrate, with each level containing memory openings, sacrificial material layers, and conductive electrode structures that are contained within the overall three-dimensional architecture. This nesting approach enables high-density storage while maintaining systematic fabrication processes
Data Source
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Figure 3A~3B
AI summary
A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stack memory openings.