GaN Integrated Circuit Matching Threshold Voltages
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Solution Overview
Problem
Existing gallium nitride (GaN) devices struggle to match the threshold voltages of enhancement mode and depletion mode devices, and they have high output capacitance, which affects their performance in high power/high frequency applications.
Innovation Solution
An integrated circuit design with an isolation region and thinner gate contact recesses in the aluminum gallium nitride (AlGaN) barrier layer is used to modulate the threshold voltages of both enhancement mode and depletion mode devices, ensuring equal absolute values and reducing gate-drain capacitance and output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard AlGaN barrier layer structure is used in GaN devices, then the devices can withstand high voltages and operate at high frequencies, but the threshold voltages of enhancement mode and depletion mode devices cannot be matched to have equal absolute values
Solution Approach 1:
The patent introduces gate contact recesses that create local thickness variations in the AlGaN barrier layer beneath the gate contacts. This local modification changes the electric field distribution and carrier concentration specifically under the gate region, enabling precise control of threshold voltage for both enhancement mode and depletion mode devices while maintaining the overall high voltage capability of the device structure.
Solution Approach 2:
The patent modifies the physical parameters of the AlGaN barrier layer by creating recesses with controlled depth and dimensions. These parameter changes in the barrier layer thickness directly affect the threshold voltage characteristics, allowing the threshold voltages of enhancement mode and depletion mode devices to be matched to have equal absolute values.
2Power
If conventional GaN device structures are used, then high power and high frequency operation is achieved, but output capacitance and gate-drain capacitance remain high
Solution Approach 1:
The gate contact recesses create localized regions with modified electrical properties beneath the gate contacts. This local modification reduces the capacitance between the gate and drain regions by changing the electric field distribution and reducing charge storage in critical regions, thereby improving switching speed while maintaining high power capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower gate-drain capacitance and output capacitance, improving the devices' performance by making the threshold voltages of enhancement and depletion mode devices equal and reducing leakage and breakdown voltage, thus enhancing their high-frequency and high-voltage capabilities.
Implementation Method 1
Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers
Implementation Method 2
a thinner region or gate contact recess in the aluminum gallium nitride (AlGaN) barrier layer under the gates that can be used to modulate the threshold voltages VTh of the enhancement mode and depletion mode devices so that the absolute values of the threshold voltages are approximately equal
Data Source
AI summary
An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.


