Sacrificial Fin Method for Sublithographic Semiconductor Device Density
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Solution Overview
Problem
The challenge lies in increasing the density of semiconductor devices using fins while maintaining desirable electrical characteristics and efficiently integrating them with planar transistors, as existing technologies face limitations in minimum fin spacing and faceting issues during silicon growth.
Innovation Solution
The method involves forming a sacrificial silicon germanium (SiGe) fin with an overlying nitride layer, trimming it to create an overhang, and growing epitaxial silicon on both sides, which reduces facet formation and allows for more controlled silicon width, ultimately resulting in two silicon fins per sacrificial fin, enabling sublithographic pitch and improved integration with planar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic methods are used to define fin spacing, then the manufacturing process is simple, but the fin spacing cannot be reduced below the lithographic limit, limiting device density
Solution Approach 1:
The method segments the fin formation process into multiple stages: first forming sacrificial fins at relaxed pitch, then using epitaxial growth to create additional fins between them. This segmentation allows the final fin pitch to be half of the original sacrificial fin pitch, effectively doubling device density while maintaining lithographic simplicity.
Solution Approach 2:
The method performs preliminary actions by first forming sacrificial fins with relaxed spacing requirements, then using these as templates for subsequent epitaxial growth. This preliminary structure enables the final fin pitch to be reduced below the original lithographic limit without requiring advanced lithography tools.
2Manufacturing precision
If silicon epitaxial growth is performed without side wall spacers, then the growth process is simpler, but faceting occurs during growth which compromises fin uniformity and width control
Solution Approach 1:
Side wall spacers are introduced as intermediary structures during the epitaxial growth process. These spacers act as physical barriers that prevent faceting by controlling the growth front, thereby maintaining fin uniformity and width control. The spacers are temporarily present during growth and can be removed or retained depending on the specific application requirements.
3Adaptability or versatility
If fins are formed with larger spacing to avoid integration issues, then planar transistor integration is easier, but device density is reduced
Solution Approach 1:
The method transitions from a single-dimension approach (direct lithographic patterning) to a two-dimension approach by combining sacrificial fin structures with epitaxial growth in the vertical dimension. This dimensional change enables simultaneous achievement of high density (through sub-lithographic pitch) and integration compatibility (through controlled fin characteristics).
Solution Approach 2:
The method changes key parameters by forming sacrificial fins with relaxed pitch parameters that are compatible with planar transistor integration, then using epitaxial growth to achieve the final high-density fin structure. This parameter transformation allows the same substrate to support both low-density integration requirements and high-density fin performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach doubles the density of semiconductor devices by achieving uniform and well-controlled silicon fin thickness and width, reducing leakage, and enhancing electrical control, while allowing for efficient integration of fin transistors with planar transistors on the same substrate.
Implementation Method 1
Epitaxial silicon is grown on the sides of the SiGe fin. During the growth, the nitride overhang functions to contain the silicon growth which has the affect of reducing or eliminating the occurrence of facets in the silicon growth.
Data Source
AI summary
A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.