Split Gate Memory Cells with Selective Cap Layer Etching
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Solution Overview
Problem
The integration of different types of field-effect transistors, such as split-gate memory cells and high-speed or high-voltage transistors, on the same substrate is challenging due to varying fabrication parameters, which affects cost, performance, and manufacturability.
Innovation Solution
A method involving the sequential etching and doping of gate layers and cap layers on a substrate to define distinct transistor gates and doped regions, allowing for the formation of split-gate memory cells and other transistors with specific thicknesses and lengths, enabling efficient integration of memory and non-memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different types of field-effect transistors are integrated on the same substrate, then device functionality and performance are improved, but fabrication complexity increases due to varying fabrication parameters
Solution Approach 1:
The substrate is divided into different regions with different gate structures. Memory cell regions use split-gate structures with select gates and memory gates, while peripheral regions use conventional single-gate structures. This segmentation allows each region to be optimized for its specific function while using a unified fabrication process flow.
Solution Approach 2:
A universal fabrication process is developed that can produce both split-gate memory cells and conventional transistors using the same sequence of steps. The process uses selective etching and doping techniques that work for both device types, eliminating the need for separate fabrication lines and reducing overall complexity.
2Manufacturing precision
If sequential etching and doping processes are used to define distinct transistor gates, then manufacturing precision is improved, but process time and complexity increase
Solution Approach 1:
Cap layers are deposited over gate layers before etching begins. These cap layers serve as protective masks during selective etching processes, ensuring precise gate definition. The preliminary placement of cap layers prevents unwanted etching and enables accurate formation of gate structures with controlled dimensions.
Solution Approach 2:
Cap layers act as intermediary protective elements during the etching and doping processes. They are selectively removed and re-applied to protect specific regions, enabling precise gate patterning without requiring complex direct-patterning techniques. This intermediary approach simplifies the overall patterning process while maintaining high precision.
3Reliability
If split-gate memory cells are fabricated with optimized select gate and memory gate heights, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
Different gate regions are given different heights through selective etching of cap layers. The select gate region retains a greater cap layer thickness for higher voltage handling, while the memory gate region has reduced cap layer thickness for optimized charge trapping. This local differentiation achieves optimal performance for each gate type using a single fabrication process.
Solution Approach 2:
The fabrication process controls gate height by varying etching parameters selectively across different regions. By adjusting etch depth, etch rate, and doping conditions in different areas, the process creates optimized gate structures with specific height parameters tailored to each gate's functional requirements without needing separate fabrication lines.
Data Source
AI summary
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.