Buried Bit Line Fabrication via Metal Silicide Formation
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Solution Overview
Problem
In three-dimensional DRAMs with vertical gates, the resistance of buried bit lines increases significantly as the line width decreases, leading to defective semiconductor devices due to voids and seams created by the CVD process, and the etch-back process can puncture through to the lower substrate, resulting in defective products.
Innovation Solution
A method for fabricating semiconductor devices involves etching a substrate to form trenches, forming an insulation layer with openings, depositing a silicon layer to gap-fill the trenches, and reacting the silicon layer with a metal layer to form a metal silicide layer as buried bit lines, which reduces resistance and prevents junction leakage by using the silicon layer as a buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the line width of buried bit lines is decreased to increase integration density, then the area occupied by tungsten is decreased, but resistance increases drastically
Solution Approach 1:
The patent uses a composite material structure consisting of a titanium nitride (TiN) layer and a tungsten (W) layer to form the buried bit line. This composite structure allows the TiN layer to provide conductive pathways that compensate for the reduced tungsten area, thereby maintaining low resistance even when the overall bit line width is decreased for higher integration density.
Solution Approach 2:
The patent changes the physical and chemical parameters of the bit line structure by introducing a TiN layer with specific thickness and conductivity parameters. By adjusting the TiN layer thickness and its electrical properties, the overall resistance of the buried bit line is controlled to remain low despite the reduced tungsten cross-sectional area.
2Ease of manufacture
If the CVD process is used to deposit tungsten layer, then the buried bit lines can be formed, but rough surfaces are created resulting in void and seam
Solution Approach 1:
The patent introduces an intermediary TiN layer between the substrate and the tungsten layer. This TiN layer serves as a buffer and seed layer that promotes more uniform tungsten deposition, reducing surface roughness and preventing void and seam formation while still allowing the CVD process to be used for manufacturing.
3Length of stationary object
If the etch-back process is performed to acquire desired bit line height, then the bit line height can be controlled, but the buried bit lines may be cut undesirably or punctured through to the lower substrate
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective insulation layer and carefully controlling the etch-back process parameters to prevent excessive removal of material. This ensures that the buried bit lines are protected from being cut or punctured through to the lower substrate while still achieving the desired bit line height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the resistance of buried bit lines, enhancing the operation speed of semiconductor devices and preventing junction leakage, thereby improving the reliability and quality of the semiconductor devices.
Implementation Method 1
forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern
Data Source
AI summary
A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.