Capacitor-less DRAM Integration on Logic Substrates
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Solution Overview
Problem
Conventional methods for integrating memory and logic devices on a common substrate face challenges such as inefficient use of active area, structural limitations, and high temperatures that hinder the combination of memory and logic, leading to reduced processor density and increased substrate size.
Innovation Solution
The method involves forming a logic device on a substrate, creating an intermediate semiconductor layer using plasma-activated bonding to reduce thermal damage, and fabricating capacitor-less DRAM cells on top of the logic device, allowing for efficient integration with reduced area consumption and lower signal lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory and logic devices are formed side-by-side in a single plane on a common substrate, then manufacturing compatibility is improved, but active area efficiency deteriorates and substrate size increases
Solution Approach 1:
The patent transitions from planar side-by-side arrangement to vertical stacking, forming memory cells above the logic device in the third dimension. This dimensional change allows both memory and logic to coexist on the same substrate without increasing lateral area, thereby resolving the contradiction between manufacturing compatibility and substrate size efficiency.
Solution Approach 2:
The patent implements nesting by placing memory cells vertically above the logic device, creating a stacked configuration where memory is embedded in the vertical space above logic. This nesting approach maximizes the use of substrate real estate by utilizing the vertical dimension, thus reducing overall substrate size while maintaining manufacturing compatibility.
2Ease of manufacture
If conventional high temperature fabrication processes are used to form memory on a substrate with logic, then memory formation is simplified, but thermal damage to logic devices increases
Solution Approach 1:
The patent segments the fabrication process into distinct temperature stages: forming logic devices at higher temperatures first, then forming memory cells at lower temperatures subsequently. This temporal and procedural segmentation allows each device type to be fabricated under optimal conditions, preventing thermal damage to logic while maintaining ease of memory formation.
Solution Approach 2:
The patent performs preliminary action by completing logic device fabrication at high temperatures before forming memory cells. This preliminary high-temperature processing establishes the logic devices first, protecting them from subsequent thermal exposure during memory formation, thereby reducing thermal damage while maintaining manufacturing simplicity.
3Ease of manufacture
If SRAM is integrated with logic devices, then fabrication process compatibility is improved, but circuit density deteriorates due to the number of required components per cell
Solution Approach 1:
The patent changes the fundamental parameter of memory cell architecture from SRAM (requiring 6 transistors per cell) to capacitor-less DRAM (requiring fewer components). This parameter change in memory cell structure reduces the number of components per cell, thereby improving circuit density while maintaining fabrication process compatibility through sequential processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of multiple logic devices and memory cells on a smaller substrate, improving processor density and reducing signal response time while maintaining efficient memory accessibility, thus addressing the inefficiencies of conventional methods.
Implementation Method 1
creating an intermediate semiconductor layer using plasma-activated bonding to reduce thermal damage
Data Source
AI summary
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.