Array Substrate Data Line Etching for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of TFT-LCDs faces challenges in achieving high-resolution and low power consumption, particularly in forming data lines with low resistivity materials like Al/Nd or Cu, which requires a transition from dry etching to wet etching, leading to increased line width differences and reduced density of data lines in the pad region, hindering high-density arrangements necessary for high-resolution displays.
Innovation Solution
A method involving sequential formation of active layer and data line metal films, followed by specific wet and dry etching processes to form data lines and electrodes, with a focus on minimizing line width differences in the pad region through controlled etching, allowing for higher density data line arrangements without the need for two wet etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wet etching process is used to form data lines with low-resistivity materials (Al/Nd or Cu), then power consumption is reduced, but line width difference increases and data line density decreases
Solution Approach 1:
The etching process is segmented into two distinct stages: first wet etching to remove the metal film and form initial data lines, then dry etching to precisely define the active layer members and channel regions. This segmentation allows each etching method to be optimized for its specific function, reducing overall line width difference while maintaining low resistance.
Solution Approach 2:
Different etching methods are applied to different regions and layers: wet etching is used where broader material removal is needed (metal film), while dry etching is used where precision is critical (active layer channel regions). This local optimization of etching quality minimizes line width variations across different structures.
2Loss of energy
If wet etching process is used to form data lines with low-resistivity materials, then resistivity is reduced, but data line density in pad region decreases
Solution Approach 1:
The patterning process is segmented into multiple photolithography and etching steps, allowing precise control over data line dimensions and spacing. This enables high-density arrangement in the pad region while maintaining the low-resistivity material benefits.
Solution Approach 2:
The data lines are formed with preliminary dimensions through the first wet etching step, then subsequently refined through dry etching. This preliminary action allows optimization of line spacing for high density before final precision definition, enabling both low resistance and high density in the pad region.
3Manufacturing precision
If two wet etching processes are used to form data lines, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent changes the etching method parameter from wet to dry for the second etching step, rather than performing two wet etching processes. This parameter change maintains manufacturing precision for line width control while reducing process complexity by eliminating the need for multiple wet etching stages and associated cleaning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a higher density arrangement of data lines in the pad region, reducing the distance between adjacent lines to about 5 μm, facilitating efficient manufacturing and maintaining low resistance, even with low-resistivity materials, thus supporting high-resolution, small-size liquid crystal displays.
Implementation Method 1
applying a photoresist layer on the data line metal film, and then exposing and developing the photoresist layer to form a first photoresist completely-remained region, a first photoresist partially-remained region and a first photoresist completely-removed region
Implementation Method 2
performing a first wet etching process to etch away the data line metal film in the first photoresist completely-removed region
Implementation Method 3
performing a first dry etching process to etch away the active layer film in the first photoresist completely-removed region
Implementation Method 4
ashing to remove the photoresist layer by a thickness of the photoresist in the first photoresist partially-remained region
Data Source
AI summary
A manufacturing method of an array substrate comprises forming gate lines, data lines, pixel electrodes, and gate electrodes, active layer members, source electrodes, drain electrodes of thin film transistors (TFTs) in pixel units in a display region and forming the gate lines and the data lines in a pad region. A process of forming the data lines, the active layer members, the source electrodes and the drain electrodes in the display region and simultaneously forming the data lines in the pad region is performed.