Array Substrate ESD Path via Gate Metal Via Holes
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Solution Overview
Problem
In the traditional manufacturing process of array substrates for ADS LCDs, the antistatic ESD component is formed too late to effectively disperse static electricity, leading to undesired effects and electrical defects.
Innovation Solution
The method involves forming a path for static electricity dispersion by coupling the gate metal layer to the first conduction layer through via holes, allowing the ESD loop to be formed in advance and reducing static electricity occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ESD component is formed during a later stage of the Array process (after the deposition of the pixel electrodes), then the manufacturing process follows the traditional sequence, but the ESD component cannot disperse static electricity during the Array process, leading to electrical defects
Solution Approach 1:
The ESD component is formed in advance during the Array process rather than in a later stage. Specifically, the ESD component is integrated with the TFT deposition process, allowing it to be present and functional before pixel electrode deposition completes. This preliminary formation enables the ESD component to actively disperse static electricity throughout the Array process, preventing electrical defects that would occur with delayed ESD component formation.
2Reliability
If the ESD component is formed in advance during the Array process, then the antistatic function is activated early to prevent static electricity damage, but this requires changing the traditional manufacturing sequence
Solution Approach 1:
The ESD component formation is merged with the existing TFT deposition process. Instead of being a separate later-stage operation, the ESD component is deposited simultaneously with or integrated into the TFT array fabrication steps. This merging approach activates the antistatic function early in the process while avoiding the need for entirely new manufacturing equipment or processes, thus reducing the complexity burden.
Solution Approach 2:
The manufacturing process is designed to serve multiple functions: the same deposition equipment and process steps that create the TFT structures also form the ESD component. This multi-functionality allows the ESD component to be integrated without requiring dedicated separate processing steps, maintaining ease of manufacture while achieving early antistatic protection.
3Ease of manufacture
If the traditional Array process is followed without early ESD component formation, then the manufacturing process remains simple, but static electricity causes undesired effects and electrical defects during the Array process
Solution Approach 1:
The ESD component is formed in advance to counteract static electricity effects before they can cause damage during the Array process. By having the ESD component present and functional during TFT deposition and pixel electrode formation, the system proactively neutralizes static charges that would otherwise accumulate and cause electrical defects, thereby eliminating harmful effects while maintaining process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electrical defects and enhances the functionality of the ESD component in dispersing electric charges, improving the manufacturing process and product quality.
Implementation Method 1
the gate metal layer is coupled to the first conduction layer through the at least one via hole to form a path for dispersing static electricity
Data Source
AI summary
Disclosed is a method for manufacturing an array substrate, comprising: step A, sequentially forming patterns of a first conduction layer, source and drain electrodes, an active layer, and an insulation layer on one side of the substrate, wherein at least one via hole is provided on the insulation layer; step B, sequentially forming a gate metal layer and a passivation layer on the substrate on which the first conduction layer, the source and drain electrodes, the active layer, and the insulation layer have been formed, wherein the gate metal layer comprises a gate electrode and a gate line, and the gate metal layer is coupled to the first conduction layer through the at least one via hole to form a path for dispersing static electricity.