Array Substrate Fabrication Reducing Masking Steps
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Solution Overview
Problem
The existing methods for fabricating array substrates for flat display devices require multiple masking processes due to the use of structures like etch stopper layers and double gates, increasing costs and complexity.
Innovation Solution
A method involving the formation of a gate electrode, a gate insulating film, a stack of polysilicon and amorphous silicon layers, source and drain electrodes, an ohmic contact layer, and a pixel electrode, where the polysilicon layer is crystallized using a UV laser beam, reducing the number of masking steps and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etch stopper layer and double gate structures are used, then device performance is improved, but manufacturing complexity and cost increase due to multiple masking processes
Solution Approach 1:
The invention removes the etch stopper layer from the traditional structure. By forming the active layer directly on the gate insulating film without an etch stopper layer, the patent eliminates the need for one masking process while maintaining device performance through the optimized double gate structure and selective etching of the active layer.
Solution Approach 2:
The invention combines the formation of the active layer and channel formation into a single process step. The active layer is formed to extend beyond the gate electrode, and the channel region is defined by selective removal of the active layer, merging what would traditionally be separate masking and etching steps into one integrated process.
2Manufacturing precision
If multiple masking processes are used for forming etch stopper layer and double gates, then structural precision is achieved, but fabrication cost and time increase
Solution Approach 1:
The active layer is formed to extend beyond the gate electrode boundaries in advance, before the channel formation step. This preliminary extension allows the channel to be defined simply by selective removal of the excess active layer, eliminating the need for additional masking processes that would otherwise be required to define the channel region with precise boundaries.
Solution Approach 2:
The active layer serves multiple functions: it provides the conductive path for current flow, defines the channel region when selectively removed, and eliminates the need for a separate etch stopper layer. This multi-functional design reduces the total number of process steps while maintaining structural precision.
3Reliability
If traditional multi-step fabrication process is used, then reliable device structure is obtained, but production efficiency decreases
Solution Approach 1:
The etch stopper layer is completely removed from the fabrication sequence. By forming the active layer directly on the gate insulating film and using selective etching to define the channel, the patent eliminates a entire layer formation and masking step, directly improving production efficiency without compromising device structure reliability.
Solution Approach 2:
The patent merges the active layer formation and channel definition into a single process sequence. The active layer is deposited to extend beyond the gate, and the channel is formed by selective removal, combining what would traditionally be separate masked steps into one efficient process flow that maintains reliable device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs, simplifies the process, and enhances device performance by improving mobility, enabling the production of high-performance panels at a lower cost for applications like AMOLED and super high definition LCDs.
Implementation Method 1
crystallized into a polysilicon layer when a UV laser beam is directed to an entire surface of the refractory metal layer
Implementation Method 2
crystallized into a polysilicon layer when a UV laser beam is directed to an entire surface of the refractory metal layer
Data Source
AI summary
The present invention relates to an array substrate for a flat display device and a method for fabricating the same, in which a number of masks is reduced for reducing a cost and improving a device performance. The array substrate includes a gate electrode formed on an insulating substrate, a gate insulating film formed on an entire surface of the insulating substrate including the gate electrode, an active layer formed on the gate insulating film opposite to the gate electrode having a stack of a polysilicon layer and an amorphous silicon layer each having a width greater than the gate electrode, a source electrode and a drain electrode separated from each other at a portion of the active layer and formed over the active layer with an ohmic contact layer disposed therebetween, an interlayer insulating film formed on an entire surface of the insulating substrate having a contact hole to expose a predetermined portion of the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole.