Solid-State Devices TRIZ Cases

Annular trench metallization reduces series resistance and potential differences, enhancing current injection efficiency in gallium nitride devices.

A display panel through-hole surrounded by a rough pattern with a metal valley prevents moisture ingress while preserving the image display area.

CxHyFz gas and water vapor post-treatment prevent aluminum corrosion while reducing source power consumption compared to CF4.

Atomic layer deposition of Al2O3 antireflection coatings on delta-doped silicon photodetectors.

A fluoropolymer wall encompasses the channel area of a thin film transistor substrate to planarize the organic semiconductor layer.

A bidirectional silicon-controlled rectifier uses a lightly-doped region to lower junction capacitance.

A display apparatus positions a second voltage line between scan and data lines to minimize signal interference.

Lateral segment arrangement eliminates viewing-angle color variation and device thickness increases caused by stacked phosphor layers in traditional LED modules.

Composite organic compounds with triazole cores and carbazole groups improve electron-hole balance, reducing electrical stress in OLEDs.

Side surfaces formed during anode patterning protect exposed signal pads from corrosion while eliminating separate masking steps.

An SOI component places MOS transistors in the supporting substrate to leverage its thermal conductivity for improved heat dissipation.

A monolithic light emitting diode array integrates circuit structures directly into the substrate to enable alternating current operation.

Rigid organometallic red emitter structure improves OLED driving voltage, luminous efficiency, and lifespan by optimizing host-dopant energy transfer.

Interlaced asymmetric support pillars prevent insulating layer buckling during sacrificial material replacement in three-dimensional memory fabrication.

A thin film transistor substrate structure uses a multi-layer insulating stack to protect the oxide semiconductor channel layer during electrode formation.

Stacked tunnel insulating film creates electron trapping sites to enhance write efficiency in nonvolatile memory.

A hybrid semiconductor chip joins a gallium arsenide Hall element to a silicon CMOS circuit via an adhesive layer.

Laser etching generates dust that causes manufacturing faults. The adhesive film captures particles to improve yield.

Embedding the non-volatile memory cell below the substrate surface prevents polishing damage to the memory structure during logic gate fabrication.

A gate insulating layer with thin and thick portions enhances capacitance per unit area in electro-optical devices.

A dual photodiode optical receiver with short-circuited potentials and laminated insulating films.

Nanoconfined polymer structures form a network within an elastomeric matrix to sustain electrical conductivity under 100% strain.

Segmented ground paths and antenna diodes protect gate layers from plasma damage while lowering inductance.

Adjusting optical distances within the resonator structure reduces required current density for white color display while maintaining luminous efficiency.

A dibrominated pyrrolo bisthiazole monomer reacts with a Turbo-Grignard reagent complex to form conjugated homopolymers.

Varying layer thicknesses and widths across the stack optimizes channel resistance, improving read operation reliability.

A eutectic alloy composition forms a backside layer on semiconductor substrates to enable reliable bonding with secondary structures.

A flat display array substrate uses laser crystallization to form active layers, simplifying the fabrication sequence.

A segmented image transport layer prevents lateral light spreading, enabling curved displays that maintain image fidelity without bulky components.

Segmented non-folding portions distribute data driving chips while connection lines surround notches to maintain electrical connectivity during folding.

A gate bus line with a locally reduced width provides high resistance for odd mode oscillation suppression.

An intermediate insulating film prevents metal atom diffusion from the molybdenum charge storage layer, ensuring reliable electric charge retention.

Modulating carrier concentration in a doped semiconductor substrate tunes the resonance frequency of a metamaterial array across the mid-infrared range.

Adding explicit capacitors across segmented diffused resistors in a voltage regulator reduces phase delay and enhances AC performance.

A separate resistor matches input impedance in an optical module, eliminating trimming processes and bias tees to reduce size.

Via hole connections integrate micro-LED elements with driving circuits on one substrate, eliminating mass transfer steps and improving alignment accuracy.

A display panel uses asymmetric sub-pixel orthographic projection shapes to mitigate diffraction light spots in under-screen camera areas.

Thermosetting and thermoplastic resin layers prevent gas entrapment and cavity deformation during modularization assembly.

Combining two specific organic compounds optimizes molecular parameters to resolve the trade-off between internal quantum efficiency and device lifetime.

A synapse memory device uses a two-transistor structure with shared source-drain areas to enable multi-level storage functionality.

A composite substrate with a metal core and insulation layers resolves the contradiction between flexibility and water resistance in display devices.

Merging gate and capacitor electrodes reduces photolithography complexity while enhancing signal transmission in organic light-emitting displays.

A semiconductor light emitting device uses a reflective resin layer inside a recess to boost optical output.

An OLED intermediate layer extends over pixel electrodes to form series connections with insulating layers.

A non-segmented U-shaped under bump metallurgy structure with independent via currents controls local carrier recombination density.

A spirally arranged electromotive component with spin orbit coupling generates voltage along a magnetized cylindrical magnetic body.

A gate conductive layer with a capping layer forms exposed wire pads for external connections.

A light-emitting device uses a crosslinked polymer hole transport layer to enhance external quantum efficiency.

A negative capacitance FinFET device with an optimized extension length reduces hysteresis.

A semiconductor diode uses a graded p-implant profile to lower holding voltage without extra processing steps.