Embedded Non-Volatile Memory Cell for Polishing Damage Prevention
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Solution Overview
Problem
In traditional memory devices, the polishing process for high-voltage/logic gate components often damages the non-volatile memory cell due to differences in gate heights, leading to structural damage and malfunction.
Innovation Solution
The non-volatile memory cell is embedded within the semiconductor substrate with its top surface coplanar or below the substrate surface, ensuring that the polishing process for the logic gate does not damage the memory cell, maintaining its integrity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the non-volatile memory cell is formed with a higher gate structure to improve its performance, then the memory cell performance is improved, but the polishing process for the logic gate will damage the memory cell structure
Solution Approach 1:
The patent applies preliminary anti-action by embedding the non-volatile memory cell structure below the substrate surface before the logic gate polishing process. This pre-positioning creates a protective configuration where the memory cell is already shielded when the polishing occurs, preventing the harmful polishing action from damaging the memory cell structure while allowing the logic gate to be properly planarized
2Object-affected harmful factors
If the non-volatile memory cell is embedded deeper in the substrate to protect it from polishing damage, then the memory cell is protected from damage, but the manufacturing complexity increases
Solution Approach 1:
The patent applies dimensionality change by transitioning the memory cell structure from a surface-level configuration to a subsurface embedded configuration. This vertical repositioning into the substrate depth dimension provides natural protection during polishing while maintaining manufacturing feasibility through controlled fabrication processes that manage the increased complexity
3Reliability
If the non-volatile memory cell is formed with a higher gate structure to achieve better performance, then the memory cell performance is improved, but the logic gate polishing process causes structural damage and malfunction
Solution Approach 1:
The patent applies preliminary anti-action by pre-embedding the memory cell structure below the substrate surface before the logic gate polishing process. This creates a protective configuration where the memory cell is already shielded when polishing occurs, preventing structural damage while maintaining manufacturing precision and achieving both performance and integrity
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.