Oxide Semiconductor TFT Substrate Structure for Etching Protection
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Solution Overview
Problem
The production of TFT substrates with oxide semiconductor channel layers faces issues such as damage during etching processes for forming source and drain electrodes, leading to degraded characteristics and increased manufacturing costs due to the need for additional photolithography processes, which can also result in poor adhesion between insulating films and reliability concerns.
Innovation Solution
A TFT substrate structure is developed with a gate electrode, a first insulating film covering the gate electrode, a channel layer of oxide semiconductor, a second insulating film, and source and drain electrodes on a third insulating film, where the oxide semiconductor film is separated from the channel layer and insulating film, reducing exposure to etching chemicals and simplifying the manufacturing process to four photolithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional photolithography processes are used to protect the oxide semiconductor channel layer during etching, then the channel layer is protected from damage, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming the protective insulating film over the oxide semiconductor layer before the etching process. This pre-formed protective layer prevents direct exposure of the channel layer to etching chemicals, eliminating the need for additional photolithography protection steps while maintaining channel layer integrity throughout subsequent manufacturing processes
2Ease of manufacture
If the oxide semiconductor channel layer is exposed to etching chemicals for forming source and drain electrodes, then the electrodes can be formed, but the channel layer is damaged and characteristics are degraded
Solution Approach 1:
The patent uses an intermediary protective insulating film that acts as a barrier between the etching chemicals and the oxide semiconductor channel layer. This intermediary layer allows the etching process to proceed for electrode formation while preventing direct contact with the channel layer, thus maintaining manufacturing ease without compromising channel layer quality
3Reliability
If additional protective layers and processes are added to protect the channel layer, then the channel layer is protected from etching damage, but the adhesion between insulating films deteriorates
Solution Approach 1:
The patent optimizes the parameters of the protective insulating film, including its thickness (50-200 nm) and material composition (silicon oxide, silicon nitride, or silicon oxynitride), to achieve the right balance between protection and adhesion. By carefully controlling these parameters, the film provides sufficient protection during etching while maintaining good adhesion to prevent film exfoliation
4Productivity
If the manufacturing process is simplified to reduce photolithography steps, then manufacturing cost and complexity are reduced, but the channel layer may be damaged during etching
Solution Approach 1:
The patent applies preliminary action by forming the protective insulating film over the oxide semiconductor layer before the etching process. This pre-formed protective layer prevents direct exposure of the channel layer to etching chemicals, eliminating the need for additional photolithography protection steps while maintaining channel layer integrity throughout subsequent manufacturing processes
Data Source
AI summary
A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.